ARM ARM1176JZF-S - Page 489

Debug
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-15
ID012310 Non-Confidential, Unrestricted Access
VCR[1] = 1 NS bit = 0 or Mode = Secure
Monitor.
X0 SBA + 0x00000004
1 0xFFFF0004
VCR[2] = 1 NS bit = 0 or Mode = Secure
Monitor.
X0 SBA + 0x00000008
1 0xFFFF0008
VCR[3] = 1 NS bit = 0 or Mode = Secure
Monitor.
X0 SBA + 0x0000000C
1 0xFFFF000C
VCR[4] = 1 NS bit = 0 or Mode = Secure
Monitor.
X0 SBA + 0x00000010
1 0xFFFF0010
VCR[6] = 1 NS bit = 0 or Mode = Secure
Monitor.
00 SBA + 0x00000018
1 0xFFFF0018
1 X Most recent Secure IRQ address
VCR[7] = 1 NS bit = 0 or Mode = Secure
Monitor.
X0 SBA +
0x0000001C
1 0xFFFF001C
VCR[10] = 1 NS bit = 0 or Mode = Secure
Monitor.
XX MBA + 0x00000008
VCR[11] = 1 NS bit = 0 or Mode = Secure
Monitor.
XX MBA + 0x0000000C
VCR[12] = 1 NS bit = 0 or Mode = Secure
Monitor.
XX MBA + 0x00000010
VCR[14] = 1 NS bit = 0 or Mode = Secure
Monitor.
XX MBA + 0x00000018
VCR[15] = 1 NS bit = 0 or Mode = Secure
Monitor.
XX MBA + 0x0000001C
VCR[25] = 1 NS bit = 1 and mode ≠ Secure
Monitor
X0 NSBA + 0x00000004
1 0xFFFF0004
VCR[26] = 1 NS bit = 1 and mode ≠ Secure
Monitor
X0 NSBA + 0x00000008
1 0xFFFF0008
VCR[27] = 1 NS bit = 1 and mode ≠ Secure
Monitor
X0 NSBA + 0x0000000C
1 0xFFFF000C
VCR[28] = 1 NS bit = 1 and mode ≠ Secure
Monitor
X0 NSBA + 0x00000010
1 0xFFFF0010
Table 13-7 Summary of debug entry and exception conditions (continued)
VCR bit NS bit, mode VE HIVECS Prefetch vector