Level One Memory System
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 7-10
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7.4 DMA
The level one DMA provides a background route to transfer blocks of data to or from the TCMs.
It is used to move large blocks, rather than individual words or small structures.
The level one DMA is initiated and controlled by accessing the appropriate CP15 registers and
instructions, see DMA control on page 3-9. This register is common to the Secure and
Non-secure world. DMA channels can be reserved for the Secure world only, or available for
both worlds, see bit [18] in the c1, Non-Secure Access Control Register on page 3-55. This bit
also determines the page tables, Secure or Non-secure, that DMA transfers use. In the
Non-secure world, the read/write access of these DMA registers depends on Non-secure Access
control register bit[18] value. Accessing these registers in the Non-secure world when not
permitted, NSAC[18] clear, results in an Undefined exception.
The value of NSAC[18] is also used during access to the Main TLB for comparison with the
NSTID of the TLB entries:
• When the channel is defined as Non-secure, NSAC[18] set, the Non-secure page tables
are used. DMA external accesses are done on Non-secure memory regions. For DMA
internal access, only TCM defined as Non-secure can be accessed.
• When the channel is defined as Secure. NSAC[18] clear, the Secure page tables are used.
The DMA external or internal access depends on the value of the NS attribute in the
corresponding descriptors. If the NS attribute in the descriptor, for external access, is
reset, the DMA channel accesses external Secure memory. If the NS attribute is set, the
DMA channel accesses external Non-secure memory. For internal access, the page
descriptor selects the TCM and the DMA performs a security permission check before
accessing the TCM.
The process specifies the internal start and end addresses and external start address, together
with the direction of the DMA. The addresses specified are Virtual Addresses, and the level one
DMA hardware includes translation of Virtual Addresses to Physical Addresses and checking
of protection attributes.
The TLB, that TLB organization on page 6-4 describes, holds the page table entries for the
DMA, and ensures that the entries in a TLB used by the DMA are consistent with the page
tables. Errors, arising from protection checks, are signaled to the processor using an interrupt.
Completion of the DMA can also be configured by software to signal the processor with an
interrupt using the same interrupt to the processor that the error uses. The status of the DMA is
read from the CP15 registers associated with the DMA.
The DMA controller is programmed using the CP15 coprocessor. DMA accesses can only be to
or from the TCM and must not be from areas of memory that can be contained in the caches.
That is, no coherency support is provided in the caches.
The processor implements two DMA channels. Only one channel can be active at a time. The
key features of the DMA system are:
• the DMA system runs in the background of processor operations
• DMA progress is accessible from software
• DMA is programmed with virtual addresses, with a MicroTLB dedicated to the DMA
function
• you can configure the DMA to work to either the instruction or data RAMs
• DMA is allocated by a privileged process, enabling User access to control the DMA.
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