ARM ARM1176JZF-S User Manual

Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-28
ID012310 Non-Confidential, Unrestricted Access
1.9 Typical pipeline operations
Figure 1-3 shows all the operations in each of the pipeline stages in the ALU pipeline, the
load/store pipeline, and the HUM buffers.
Figure 1-3 Typical operations in pipeline stages
Figure 1-4 shows a typical ALU data processing instruction. The processor does not use the
load/store pipeline or the HUM buffer.
Figure 1-4 Typical ALU operation
Figure 1-5 on page 1-29 shows a typical multiply operation. The MUL instruction can loop in
the MAC1 stage until it has passed through the first part of the multiplier array enough times.
The MUL instruction progresses to MAC2 and MAC3 where it passes through the second half
of the array once to produce the final result.
MAC1
1st
multiply
stage
Sh
Shifter
operation
Ex1
1st fetch
stage
Fe1 Fe2 De Iss WBex
DC1 DC2
2nd fetch
stage
Instruction
decode
Register
read and
instruction
issue
Base
register
writeback
Data
address
calculation
First stage
of data
cache
access
Second
stage of
data cache
access
Writeback
from LSU
Load miss
waits
ADD WBls
Common decode pipeline
MAC2
2nd
multiply
stage
ALU
Calculate
writeback
value
Ex2
MAC3
3rd
multiply
stage
Sat
Saturation
Ex3
ALU
pipeline
Load/store
pipeline
Hit under
miss
Multiply
pipeline
MAC3
Not used
Sat
Saturation
Ex3
MAC2
Not used
ALU
Calculate
writeback
value
Ex2
MAC1
Not used
Sh
Shifter
operation
Ex1
1st fetch
stage
Fe1 Fe2 De Iss WBex
2nd fetch
stage
Instruction
decode
Register
read and
instruction
issue
Base
register
writeback
Not used
Common decode pipeline
Not used
ADD DC1
Not used
DC2
Not used Not used
WBls
ALU
pipeline
Load/store
pipeline
Hit under
miss
Multiply
pipeline

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English