System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-39
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For example:
MRC p15, 0, <Rd>, c0, c2, 1 ;Read Instruction Set Attributes Register 1
c0, Instruction Set Attributes Register 2
The purpose of the Instruction Set Attributes Register 2 is to provide information about the
instruction set that the processor supports beyond the basic set.
The Instruction Set Attributes Register 2 is:
•in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-23 shows the bit arrangement for Instruction Set Attributes Register 2.
Figure 3-23 Instruction Set Attributes Register 2 format
Table 3-32 lists how the bit values correspond with the Instruction Set Attributes Register 2
functions.
- - - - - --
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
-
Table 3-32 Instruction Set Attributes Register 2 bit functions
Bits
Field
name
Function
[31:28] - Indicates support for reversal instructions.
0x1
, ARM1176JZF-S processors support REV, REV16, and REVSH.
[27:24] - Indicates support for PSR instructions.
0x1
, ARM1176JZF-S processors support MRS and MSR exception return instructions for
data-processing.
[23:20] - Indicates support for advanced unsigned multiply instructions.
0x2
, ARM1176JZF-S processors support:
• UMULL and UMLAL
• UMAAL.
[19:16] - Indicates support for advanced signed multiply instructions.
0x3
, ARM1176JZF-S processors support:
• SMULL and SMLAL
• SMLABB, SMLABT, SMLALBB,SMLALBT, SMLALTB, SMLALTT, SMLATB,
SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB,
SMULWT, and Q flag in PSRs
• SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX,
SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX,
SMUSD, and SMUSDX.
[15:12] - Indicates support for multiply instructions.
0x1
, ARM1176JZF-S processors support MLA.
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