Unaligned and Mixed-endian Data Access Support
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-12
ID012310 Non-Confidential, Unrestricted Access
Figure 4-13 Store word, big-endian
If strict alignment fault checking is enabled and Address bits [1:0] are not zero, then a Data
Abort is generated and the MMU returns a Misaligned fault in the Fault Status Register.
4.3.14 Load double, load multiple, load coprocessor (little-endian, E = 0)
The access is treated as a series of incrementing aligned word loads from memory. The data is
treated as load word data, see Load word, little-endian on page 4-10, where the lowest two
address bits are zeroed. If strict alignment fault checking is enabled and effective Address
bits[1:0] are not zero, then a Data Abort is generated and the MMU returns an Alignment fault
in the Fault Status Register.
4.3.15 Load double, load multiple, load coprocessor (big-endian, E=1)
The access is treated as a series of incrementing aligned word loads from memory. The data is
treated as load word data, see Load word, big-endian on page 4-11, where the lowest two
address bits are zeroed. If strict alignment fault checking is enabled and effective Address
bits[1:0] are not zero, then a Data Abort is generated and the MMU returns an Alignment fault
in the Fault Status Register.
4.3.16 Store double, store multiple, store coprocessor (little-endian, E=0)
The access is treated as a series of incrementing aligned word stores to memory. The data is
treated as store word data, see Store word, little-endian on page 4-11, where the lowest two
address bits are zeroed. If strict alignment fault checking is enabled and effective Address
bits[1:0] are not zero, then a Data Abort is generated and the MMU returns an Alignment fault
in the Fault Status Register.
4.3.17 Store double, store multiple, store coprocessor (big-endian, E=1)
The access is treated as a series of incrementing aligned word stores to memory. The data is
treated as store word data, see Store word, big-endian, where the lowest two address bits are
zeroed. If strict alignment fault checking is enabled and effective Address bits[1:0] are not zero,
then a Data Abort is generated and the MMU returns an Alignment fault in the Fault Status
Register.
Register
31 23 15 7 0
B0 B1 B2 B3
B1
B0
Memory
Address
A[31:0]
70
B2
+1
lsbyte
msbyte
B3
+2
+3
To Next Page
Loading...
Need help?
General
