ARM ARM1176JZF-S - Table 3-145 Results of Access to the System Validation Operations Register

System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-143
ID012310 Non-Confidential, Unrestricted Access
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Table 3-145 lists the results of attempted access for each mode. Access in Secure User mode and
in the Non-secure world depends on the V bit, see c15, Secure User and Non-secure Access
Validation Control Register on page 3-132.
To use the System Validation Operations Register write CP15 with <Rd> set to SBZ and:
• Opcode_1 set to:
— 0, Start reset, interrupt, or fast interrupt counters
— 1, Start external debug request counter
— 2, Stop reset, interrupt, or fast interrupt counters
— 3, Stop external debug request counter.
• CRn set to c15
• CRm set to c13
• Opcode_2 set to:
— 1, Reset counter
— 2, Interrupt counter
— 3, Reset and interrupt counters
— 4, Fast interrupt counter
— 5, Reset and fast interrupt counters
— 6, Interrupt and fast interrupt counters
— 7, Reset, interrupt and fast interrupt counters
— Any value, External debug request counter.
For example:
MCR p15, 0, <Rd>, c15, c13, 1 ; Start reset counter
MCR p15, 0, <Rd>, c15, c13, 2 ; Start interrupt counter
MCR p15, 0, <Rd>, c15, c13, 3 ; Start reset and interrupt counters
MCR p15, 0, <Rd>, c15, c13, 4 ; Start fast interrupt counter
MCR p15, 0, <Rd>, c15, c13, 5 ; Start reset and fast interrupt counters
MCR p15, 0, <Rd>, c15, c13, 6 ; Start interrupt and fast interrupt counters
MCR p15, 0, <Rd>, c15, c13, 7 ; Start reset, interrupt and fast interrupt counters
MCR p15, 1, <Rd>, c15, c13, 0 ; Start external debug request counter
MCR p15, 2, <Rd>, c15, c13, 1 ; Stop reset counter
MCR p15, 2, <Rd>, c15, c13, 2 ; Stop interrupt counter
MCR p15, 2, <Rd>, c15, c13, 3 ; Stop reset and interrupt counters
MCR p15, 2, <Rd>, c15, c13, 4 ; Stop fast interrupt counter
MCR p15, 2, <Rd>, c15, c13, 5 ; Stop reset and fast interrupt counters
MCR p15, 2, <Rd>, c15, c13, 6 ; Stop interrupt and fast interrupt counters
MCR p15, 2, <Rd>, c15, c13, 7 ; Stop reset, interrupt and fast interrupt counters
MCR p15, 3, <Rd>, c15, c13, 0 ; Stop external debug request counter
Table 3-145 Results of access to the System Validation Operations Register
V bit
Secure Privileged Non-secure Privileged User
Read Write Read Write Read Write
0 Unpredictable Data Undefined
exception
Undefined exception Undefined
exception
Undefined exception
1 Unpredictable Data Unpredictable Data Unpredictable Data