Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-38
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8.7 Endianness
ARM1176JZF-S processors can be configured in one of three endianness modes of operation
using the U, B, and E bits of the CP15 c1 Control Register, see Mixed-endian access support on
page 4-17.
BE-8 refers to byte-invariant big-endian configuration on 16-bit, halfword, and 32-bit, word,
quantities only.
Even if the data and DMA ports are 64-bit wide, the accesses issued on these ports still have to
be considered as two 32-bit accesses in parallel. The BE-8 configuration does not apply to the
64-bit data but on the two 32-bit words forming these 64-bit data.
The AXI protocol does not support 32-bit word-invariant big-endian, BE-32, accesses.
Therefore, in this configuration the ARM1176JZF-S processor issues byte-invariant big-endian,
BE-8, accesses on the four ports by swizzling the byte lanes and the byte strobes as Figure 8-4
shows.
Figure 8-4 Swizzling of data and strobes in BE-32 big-endian configuration
Note
If you want to configure the processor for BE-32 mode, it is strongly recommended that you use
the BIGENDINIT and UBITINIT input pins. See c1, Control Register on page 3-44 bit [7].
DATA[63:56]
DATA[55:48]
DATA[47:40]
DATA[39:32]
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
DATA[63:56]
DATA[55:48]
DATA[47:40]
DATA[39:32]
DATA[31:24]
DATA[23:16]
DATA[15:8]
DATA[7:0]
STRB[7]
STRB[6]
STRB[5]
STRB[4]
STRB[3]
STRB[2]
STRB[1]
STRB[0]
STRB[7]
STRB[6]
STRB[5]
STRB[4]
STRB[3]
STRB[2]
STRB[1]
STRB[0]
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