System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-11
ID012310 Non-Confidential, Unrestricted Access
• interrupts
• fast interrupts
• external debug requests.
The system validation registers consist of four 32-bit read/write registers. Figure 3-8 shows the
arrangement of registers.
Figure 3-8 System validation registers
The System Validation Counter Register and System Validation Operations Register reuse the
Cycle Counter Register, Count Register 0, and Count Register 1, see System performance
monitor on page 3-10, to schedule resets, interrupts and fast interrupts respectively. External
debug requests are scheduled using an additional 6 bit counter that is not used by the System
performance monitor registers.
Each of the four counters counts upwards, and when the counter overflows, the corresponding
event occurs. To the core, the events are indistinguishable from ordinary external events. The
System Validation Registers provide functions for loading the counter registers with the
required number of clock cycles before the event occurs, and starting, stopping and clearing the
counters, to return them to their System performance monitor functionality.
The System Validation Registers are usually only accessible from Secure privileged modes, but
a Secure User and Non-secure Access Validation Control Register is provided to permit access
to the System Validation Registers from User modes and Non-secure modes.
The System Validation Cache Size Mask Register masks the physical size of the caches and
TCMs to make their size appear different to the processor. You can use this in validation by
simulation, but you must not use it in a manufactured device because it can corrupt correct
operation of the processor.
Read-only Read/write
c12
4
c13
c15
Write-only
Secure User and Non-secure Access Validation Control Register
System Validation
Counter Registers
System
Validation
Operations
Registers
0
c90
Opcode_2Opcode_1 CRmCRn
System Validation Cache Size Mask Register
5
6
7
Reset counter
Interrupt counter
Fast interrupt counter
External debug request counter
0
c13
1
c13
2
c13
3
2
3
4
5
1
6
7
2
3
4
5
1
6
7
Start reset counter
Start interrupt counter
Start reset and interrupt counters
Start fast interrupt counter
Start reset and fast interrupt counters
Start interrupt and fast interrupt counters
Start reset, interrupt and fast interrupt counters
Start external debug request counter
Stop reset counter
Stop interrupt counter
Stop reset and interrupt counters
Stop fast interrupt counter
Stop reset and fast interrupt counters
Stop interrupt and fast interrupt counters
Stop reset, interrupt and fast interrupt counters
Stop external debug request counter
Accessible in User mode
c14
0
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