Memory Management Unit
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-38
ID012310 Non-Confidential, Unrestricted Access
Figure 6-5 Backwards-compatible second-level descriptor format
For extended small page table entries without a TEX field you must use the value b000. For
details of TEX encodings see C and B bit, and type extension field encodings on page 6-14.
Note
For any Supersection description in a first-level page table, and any Large page description in a
second-level page table:
• you must repeat the description in 16 consecutive page table locations
• the first description must occur on a 16-word boundary
For more information see the ARM Architecture Reference Manual.
Figure 6-6 shows an overview of the section, supersection, and page translation process using
backwards-compatible descriptors.
Figure 6-6 Backwards-compatible section, supersection, and page translation
SBZ
TEX AP3 B
B
1Large page base address AP2
AP1
AP0 C 0
0Small page base address AP3 AP2 AP1 AP0 C B 1
1Extended small page base address TEX AP C 1
Translation fault
Large page (64KB)
Small page
(4KB)
0Ignored
31 16 15 12 11 10 9 8 7 6 5 4 3 2 1 0
0
Extended small
page (4KB)
16KB subpage
Invalid
Invalid
Indexed by
VA[19:12]
Base address
from L2D[31:12]
Indexed by
VA[11:0]
Indexed by
VA[15:0]
Base address
from L2D[31:16]
First level
page table
Coarse page
table
4KB extended
small page
64KB large page
Translation
table base
Indexed by
VA[31:20]
31 0
31 0
31 0
Base address
from L1D[31:24]
Indexed by
VA[23:0]
16MB
supersection
Base address
from L1D[31:20]
Indexed by
VA[19:0]
1MB section
(bit 18 = 0)
Base address
from L1D[31:10]
16KB subpage
16KB subpage
16KB subpage
4KB small page
1KB subpage
31 0
1KB subpage
1KB subpage
1KB subpage
Indexed by
VA[11:0]
Base address
from L2D[31:12]
01
00
00
01
10
11
10
(bit 18 = 1) 10
To Next Page
Loading...
Need help?
General
