System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-33
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Table 3-23 lists the results of attempted access for each mode.
To use the Memory Model Feature Register 1 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 5.
For example:
MRC p15, 0, <Rd>, c0, c1, 5 ;Read Memory Model Feature Register 1.
c0, Memory Model Feature Register 2
The purpose of the Memory Model Feature Register 2 is to provide information about the
memory model, memory management, cache support, and TLB operations of the processor.
The Memory Model Feature Register 2 is:
•in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-19 on page 3-34 shows the bit arrangement for Memory Model Feature Register 2.
[11:8] - Indicates support for level one cache line maintenance operations by Set/Way, Harvard architecture.
0x3
, ARM1176JZF-S processors support:
• clean data cache line by Set/Way
• clean and invalidate data cache line by Set/Way
• invalidate data cache line by Set/Way
• invalidate instruction cache line by Set/Way.
[7:4] - Indicates support for level one cache line maintenance operations by MVA, unified architecture.
0, no support in ARM1176JZF-S processors.
[3:0] - Indicates support for level one cache line maintenance operations by MVA, Harvard architecture.
0x2
, ARM1176JZF-S processors support:
• clean data cache line by MVA
• invalidate data cache line by MVA
• invalidate instruction cache line by MVA
• clean and invalidate data cache line by MVA
• invalidation of branch target buffer by MVA.
Table 3-22 Memory Model Feature Register 1 bit functions (continued)
Bits
Field
name
Function
Table 3-23 Results of access to the Memory Model Feature Register 1
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Undefined exception Data Undefined exception Undefined exception
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