ARM ARM1176JZF-S User Manual

System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-135
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The Performance Monitor Control Register:
• controls the events that Count Register 0 and Count Register 1 count
• indicates the counter that overflowed
• enables and disables the report of interrupts
• extends Cycle Count Register counting by six more bits, cycles between counter rollover
= 2
38
• resets all counters to zero
• enables the entire performance monitoring mechanism.
Table 3-137 lists the events that can be monitored using the Performance Monitor Control
Register.
[2] C Cycle Counter Register Reset. Reset on write, Unpredictable on read:
0 = No action, reset value
1 = Reset the Cycle Counter Register to
0x0 .
[1] P Count Register 1 and Count Register 0 Reset. Reset on write, Unpredictable on read:
0 = No action, reset value
1 = Reset both Count Registers to 0x0 .
[0] E Enable all counters:
0 = All counters disabled, reset value
1 = All counters enabled.
Table 3-136 Performance Monitor Control Register bit functions (continued)
Bits Field name Function
Table 3-137 Performance monitoring events
EVNTBUS
bit position
Event
number
Event definition
-
0xFF An increment each cycle.
-
0x26 Procedure return instruction executed and return address predicted incorrectly. The
procedure return address was restored to the return stack following the prediction
being identified as incorrect.
-
0x25 Procedure return instruction executed and return address predicted. The procedure
return address was popped off the return stack and the core branched to this address.
-
0x24 Procedure return instruction executed. The procedure return address was popped off
the return stack.
-
0x23 Procedure call instruction executed. The procedure return address was pushed on to
the return stack.
-
0x22 If both ETMEXTOUT[0] and ETMEXTOUT[1] signals are asserted then the count
is incremented by two. If either signal is asserted then the count increments by one.
-
0x21 ETMEXTOUT[1] signal was asserted for a cycle.
-
0x20 ETMEXTOUT[0] signal was asserted for a cycle.
[19]
0x12 Write Buffer drained because of a Data Synchronization Barrier operation or
Strongly Ordered operation.

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English