Signal Descriptions
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. A-15
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A.8 ETM interface signals
Table A-13 lists the ETM interface signals.
Table A-13 ETM interface signals
Name Direction Description
ETMDA[31:3] Output ETM data address.
ETMDACTL[17:0] Output ETM data control, address phase.
ETMDD[63:0] Output ETM data.
ETMDDCTL[3:0] Output ETM data control, data phase.
ETMEXTOUT[1:0] Input ETM external event to be monitored.
ETMIA[31:0] Output ETM instruction address.
ETMIACTL[17:0] Output ETM instruction control.
ETMIASECCTL[1:0] Output TrustZone trace information.
ETMIARET[31:0] Output ETM return instruction address.
ETMPADV[2:0] Output ETM pipeline advance.
ETMPWRUP Input When HIGH, indicates that the ETM is powered up. When LOW, logic
supporting the ETM must be clock gated to conserve power.
nETMWFIREADY Input When LOW, indicates ETM can accept Wait For Interrupt.
ETMCPADDRESS[14:0] Output Coprocessor address.
ETMCPSECCTL[1:0] Output Coprocessor Non-secure access and prohibited trace.
ETMCPCOMMIT Output Coprocessor commit.
ETMCPENABLE Output Coprocessor interface enable.
ETMCPRDATA[31:0] Input Coprocessor read data.
ETMCPWDATA[31:0] Output Coprocessor write data.
ETMCPWRITE Output Coprocessor write control.
EVNTBUS[19:0] Output System metrics event bus.
WFIPENDING Output Indicates a Pending Wait For Interrupt. Handshakes with
nETMWFIREADY.
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