EasyManua.ls Logo

ARM ARM1176JZF-S - Cacheable Write-Through or Noncacheable STM4 to Word 0, 1, 2, 3, or 4; Cacheable Write-Through or Noncacheable STM4 to Word 5, 6, or 7; Cacheable Write-Through or Noncacheable STM5 to Word 0, 1, 2, or 3; Cacheable Write-Through or Noncacheable STM5 to Word 4, 5, 6, or 7

Default Icon
759 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-30
ID012310 Non-Confidential, Unrestricted Access
8.5.27 Cacheable Write-Through or Noncacheable STM4
Table 8-52 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for STM4s to words 0 to 4 over the Data Read/Write Interface.
An STM4 to words 5 to 7 is split into two operations as shown in Table 8-53.
8.5.28 Cacheable Write-Through or Noncacheable STM5
Table 8-54 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for STM5s to words 0 to 3 over the Data Read/Write Interface.
An STM5 to words 4 to 7 is split into two operations as shown in Table 8-55.
Table 8-52 Cacheable Write-Through or Noncacheable STM4 to word 0, 1, 2, 3, or 4
Address[4:0]
AWADDRR
W
AWBURSTR
W
AWSIZERW AWLENRW First WSTRBRW
0x00
, word 0
0x00
Incr 64-bit 2 data transfers b1111 1111
0x04
, word 1
0x04
Incr 32-bit 4 data transfers b11110000
0x08
, word 2
0x08
Incr 64-bit 2 data transfers b11111111
0x0C
, word 3
0x0C
Incr 32-bit 4 data transfers b11110000
0x10
, word 4
0x10
Incr 64-bit 2 data transfers b11111111
Table 8-53 Cacheable Write-Through or Noncacheable STM4 to word 5, 6, or 7
Address[4:0] Operations
0x14
, word 5 STM3 to
0x14
+ STR to
0x00
0x18
, word 6 STM2 to
0x18
+ STM2 to
0x00
0x1C
, word 7 STR to
0x1C
+ STM3 to
0x00
Table 8-54 Cacheable Write-Through or Noncacheable STM5 to word 0, 1, 2, or 3
Address[4:0]
AWADDRR
W
AWBURSTR
W
AWSIZERW AWLENRW First WSTRBRW
0x00
, word 0
0x00
Incr 32-bit 5 data transfers b0000 1111
0x04
, word 1
0x04
Incr 32-bit 5 data transfers b1111 0000
0x08
, word 2
0x08
Incr 32-bit 5 data transfers b0000 1111
0x0C
, word 3
0x0C
Incr 32-bit 5 data transfers b1111 0000
Table 8-55 Cacheable Write-Through or Noncacheable STM5 to word 4, 5, 6, or 7
Address[4:0] Operations
0x10
, word 4 STM4 to
0x10
+ STR to
0x00

Table of Contents

Related product manuals