System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-76
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Example 3-1 shows how to use Clean and Invalidate Data Cache Line with Set
and Index to clean and invalidate one whole cache way, in this example, way 3.
The example works with any cache size because it reads the cache size from the
Cache Type Register.
Example 3-1 Clean and Invalidate Data Cache Line with Set and Index
MRC p15,0,R0,c0,c0,1 ; Read cache type reg
AND R0,R0,#0x1C0000 ; Extract D cache size
MOV R0,R0, LSR #18 ; Move to bottom bits
ADD R0,R0,#7 ; Get Index loop max
MOV r1,#3:SHL:30 ; Set up Set = 3
MOV R2,#0 ; Set up Index counter
MOV R3,#1
MOV R3,R3, LSL R0 ; Set up Index loop max
index_loop
ORR R4,R2,r1 ; Set and Index format
MCR p15,0,R4,c7,c14,2 ; Clean&inval D cache line
ADD R2,R2,#1:SHL:5 ; Increment Index
CMP R2,R3 ; Done all index values?
BNE index_loop ; Loop until done
Address ranges
Table 3-73 lists the instructions and operations that you can use to clean and
invalidate the address ranges in cache.
The operations in Table 3-73 can only be performed using an MCRR or MCRR2
instruction, and all other operations to these registers are ignored.
The
End Address
and
Start Address
in Table 3-73 is the true VA before any
modification by the Fast Context Switch Extension (FCSE). This address is
translated by the FCSE logic. Each of the range operations operates between
cache lines containing the
Start Address
and the
End Address
, inclusive of
Start
Address
and
End Address
.
MCR p15, 0, <Rd>, c7, c13, 1
MVA Prefetch Instruction Cache Line
MCR p15, 0, <Rd>, c7, c14, 1
MVA Clean and Invalidate Data Cache Line, using MVA
MCR p15, 0, <Rd>, c7, c14, 2
Set/Index Clean and Invalidate Data Cache Line, using Index
Table 3-73 Cache operations for address ranges
Instruction Data Function
MCRR p15,0,<End Address>,<Start Address>,c5
VA Invalidate Instruction Cache Range
MCRR p15,0,<End Address>,<Start Address>,c6
VA Invalidate Data Cache Range
MCRR p15,0,<End Address>,<Start Address>,c12
VA
Clean Data Cache Range
a
a. This operation is accessible in both User and privileged modes of operation. All other operations listed
here are only accessible in privileged modes of operation.
MCRR p15,0,<End Address>,<Start Address>,c14
VA Clean and Invalidate Data Cache Range
Table 3-72 Cache operations for single lines (continued)
Instruction Data Function
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