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Unaligned and Mixed-endian Data Access Support

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4.2 Unaligned access support

Instructions must always be aligned as follows:

• ARM 32-bit instructions must be word boundary aligned, Address [1:0] = b00

• Thumb 16-bit instructions must be halfword boundary aligned, Address [0] = 0.

The following sections describe unaligned data access support:

• Legacy support

• ARMv6 extensions

• Legacy and ARMv6 configurations on page 4-4

• Legacy data access in ARMv6 (U=0) on page 4-4

• Support for unaligned data access in ARMv6 (U=1) on page 4-4

• ARMv6 unaligned data access restrictions on page 4-5.

4.2.1 Legacy support

For ARM architectures prior to ARM architecture v6, data access to non-aligned word and

halfword data was treated as aligned from the memory interface perspective. That is, the address

is treated as truncated with Address[1:0], treated as zero for word accesses, and Address[0]

treated as zero for halfword accesses.

Load single word ARM instructions are also architecturally defined to rotate right the word

aligned data transferred by a non word-aligned access, see the ARM Architecture Reference

Manual.

Alignment fault checking is specified for processors with architecturally compliant Memory

Management Units (MMUs), under control of CP15 Register c1 A control bit, bit 1. When a

transfer is not naturally aligned to the size of data transferred a Data Abort is signaled with an

Alignment fault status code, see ARM Architecture Reference Manual for more details.

4.2.2 ARMv6 extensions

ARMv6 adds unaligned word and halfword load and store data access support. When enabled,

one or more memory accesses are used to generate the required transfer of adjacent bytes

transparently, apart from a potentially greater access time where the transaction crosses a

word-boundary.

The memory management specification defines a programmable mechanism to enable

unaligned access support. This is controlled and programmed using the CP15 Register c1 U

control bit, bit 22.

Non word-aligned for load and store multiple/double, semaphore, synchronization, and

coprocessor accesses always signal Data Abort with Alignment Faults Status Code when the U

bit is set.

Strict alignment checking is also supported in ARMv6, under control of the CP15 Register c1

A control bit, bit [1], and signals a Data Abort with Alignment Fault Status Code if a 16-bit

access is not halfword aligned or a single 32-bit load/store transfer is not word aligned.

ARMv6 alignment fault detection is a mandatory function associated with address generation

rather than optionally supported in external memory management hardware.

ARM ARM1176JZF-S User Manual

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