Debug Test Access Port
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-9
ID012310 Non-Confidential, Unrestricted Access
All ARM semiconductor partner-specific devices must be identified by
manufacturer ID numbers of the form shown in c0, Main ID Register on
page 3-20.
Length 32 bits.
Operating mode When the ID code instruction is current, the shift section of the device ID
register is selected as the serial path between DBGTDI and DBGTDO.
There is no parallel output from the ID register. The 32-bit device ID code
is loaded into this shift section during the Capture-DR state. This is shifted
out during Shift-DR, least significant bit first, while a don’t care value is
shifted in. The shifted-in data is ignored in the Update-DR state.
Order Figure 14-4 shows the order of bits in the ID code register.
Figure 14-4 Device ID code register bit order
14.6.3 Instruction register
Purpose Holds the current DBGTAP controller instruction.
Length 5 bits.
Operating mode When in Shift-IR state, the shift section of the instruction register is
selected as the serial path between DBGTDI and DBGTDO. At the
Capture-IR state, the binary value b00001 is loaded into this shift section.
This is shifted out during Shift-IR, least significant bit first, while a new
instruction is shifted in, least significant bit first. At the Update-IR state,
the value in the shift section is loaded into the instruction register so it
becomes the current instruction. On DBGTAP reset, the IDcode becomes
the current instruction.
Order Figure 14-5 shows the order of bits in the instruction register.
Figure 14-5 Instruction register bit order
14.6.4 Scan chain select register (SCREG)
Purpose Holds the currently active scan chain number.
DBGTDI DBGTDO
Data[31:0]
1
Version
31 28 27 12 11 1 0
Part number Manufacturer ID
0b00001
DBGTDI DBGTDO
Data[4:0]
IR[4:0]
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