System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-23
ID012310 Non-Confidential, Unrestricted Access
Table 3-7 lists the results of attempted access for each mode.
To use the Cache Type Register read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c0
• Opcode_2 set to 1.
For example:
MRC p15,0,<Rd>,c0,c0,1; returns cache details
Table 3-8, for example, lists the Cache Type Register values for an ARM1176JZF-S processor
with:
• separate instruction and data caches
• cache size = 16KB
• associativity = 4-way
• line length = eight words
• caches use write-back, CP15 c7 for cache cleaning, and Format C for cache lockdown.
Table 3-7 Results of access to the Cache Type Register
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Undefined exception Data Undefined exception Undefined exception
Table 3-8 Example Cache Type Register format
Bits Field name Value Behavior
[31:29] Reserved b000
[28:25] Ctype b1110
[24] S b1 Harvard cache
[23] Dsize P b0
[22] Reserved b0
[21:18] Size b0101 16KB
[17:15] Assoc b010 4-way
[14] M b0
[13:12] Len b10 8 words per line, 32 bytes
[11] Isize P b0
[10] Reserved b0
[9:6] Size b0101 16KB
[5:3] Assoc b010 4-way
[2] M b0
[1:0] Len b10 8 words per line, 32 bytes
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