System Control Coprocessor
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[23:12] Dsize Provides information about the size and construction of the Data cache.
Note
The ARM1176JZF-S processor does not support cache sizes of less than 4KB.
[23] P bit The P, Page, bit indicates restrictions on page allocation for bits [13:12] of the VA
For ARM1176JZF-S processors, the P bit is set if the cache size is greater than 16KB. For
more details see Restrictions on page table mappings page coloring on page 6-41.
0 = no restriction on page allocation.
1 = restriction applies to page allocation.
[22] - 0
[21:18] Size The Size field indicates the cache size in conjunction with the M bit.
b0000 = 0.5KB cache, not supported
b0001 = 1KB cache, not supported
b0010 = 2KB cache, not supported
b0011 = 4KB cache
b0100 = 8KB cache
b0101 = 16KB cache
b0110 = 32KB cache
b0111 = 64KB cache
b1000 = 128KB cache, not supported.
[17:15] Assoc b010, indicates that the ARM1176JZF-S processor has 4-way associativity. All other values
for Assoc are reserved.
[14] M bit Indicates the cache size and cache associativity values in conjunction with the Size and Assoc
fields.
In the ARM1176JZF-S processor the M bit is set to 0, for the Data and Instruction Caches.
[13:12] Len b10, indicates that ARM1176JZF-S processor has a cache line length of 8 words, that is 32
bytes. All other values for Len are reserved.
[11:0] Isize Provides information about the size and construction of the Instruction cache.
[11] P The functions of the Isize bit fields are the same as the equivalent Dsize bit fields and the Isize
values have the corresponding meanings.
[10] -
[9:6] Size
[5:3] Assoc
[2] M
[1:0] Len
Table 3-6 Cache Type Register bit functions (continued)
Bits Field name Function
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