Introduction to the VFP coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-9
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coprocessor in the Writeback stage. Data is written to the register file in the Writeback stage,
and available for forwarding to data processing operations in the same cycle. Figure 18-3 shows
the structure of the LS pipeline.
Figure 18-3 LS pipeline
LS pipeline instructions
The LS pipeline executes the following instructions:
FLD Load a single-precision, double-precision, or 32-bit integer value from memory
to the VFP11 register file.
FLDM Load up to 32 single-precision or integer values or 16 double-precision values
from memory to the VFP11 register file.
FST Store a single-precision, double-precision, or 32-bit integer value from the VFP11
register file to memory.
FSTM Store up to 32 single-precision or integer values or 16 double-precision values
from the VFP11 register file to memory.
FMSR Move a single-precision or integer value from an ARM11 register to a VFP11
single-precision register.
FMRS Move a single-precision or integer value from a VFP11 single-precision register
to an ARM11 register.
FMDHR Move an ARM11 register value to the upper half of a VFP11 double-precision
register.
FMDLR Move an ARM11 register value to the lower half of a VFP11 double-precision
register.
FMRDH Move the upper half of a double-precision value from a VFP11 double-precision
register to an ARM11 register.
ExecuteDecodeFetch
AVFPINSTR
(instruction
bus)
Fd
Fm
Fn
Store
Load
Read
port Fd
Read
port Fn
Store
data
bus
Register
file: read
and
format
muxes
Read
port Fm
FMAC writeback
Memory 2 Writeback
Register
file: write
and
format
muxes
DS forward
Load forward
Load data bus
FMAC forward
DS writeback
Register
address
generation
Memory 1Issue
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