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VFP Instruction Execution

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21.5 Hazards

The VFP11 coprocessor incorporates full hazard detection with a fully-interlocked pipeline

protocol. No compiler scheduling is required to avoid hazard conditions. The source and

destination scoreboards process interlocks caused by unavailable source or destination registers

or by unavailable data. The scoreboards stall instructions until all data operands and destination

registers are available before the instruction is issued to the instruction pipeline.

The determination of hazards and interlock conditions is different in full-compliance mode and

RunFast mode. RunFast mode guarantees no bounce conditions and has a less strict hazard

detection mechanism, enabling instructions to begin execution earlier than in full-compliance

mode.

There are two VFP11 pipeline hazards:

• A data hazard is a combination of instructions that creates the potential for operands to be

accessed in the wrong order.

—A Read-After-Write (RAW) data hazard occurs when the pipeline creates the

potential for an instruction to read an operand before a prior instruction writes to it.

It is a hazard to the intended read-after-write operand access.

—A Write-After-Read (WAR) data hazard occurs when the pipeline creates the

potential for an instruction to write to a register before a prior instruction reads it. It

is a hazard to the intended write-after-read operand access.

—A Write-After-Write (WAW) data hazard occurs when the pipeline creates the

potential for an instruction to write to a register before a prior instruction writes to

it. It is a hazard to the intended write-after-write operand access.

• Resource hazard. See Resource hazards on page 21-17.

ARM ARM1176JZF-S User Manual

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