ARM ARM1176JZF-S User Manual

Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-25
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1.7 Configurable options
Note
These options are configurable features of your ARM1176JZF-S processor implementation.
They are not programmable options of the implemented device.
Table 1-4 lists the ARM1176JZF-S processor configurable options.
In addition, the form of the BIST solution for the RAM blocks in the ARM1176JZF-S design is
determined when the processor is implemented. For details, see the ARM11 Memory Built-In
Self Test Controller Technical Reference Manual.
Table 1-5 lists the default configuration of ARM1176JZF-S processor.
Table 1-4 Configurable options
Feature Range of options
IEM support Yes or No
Cache way size 1KB, 2KB, 4KB, 8KB, or 16KB
Number of cache ways 4, not configurable
TCM block size 4KB, 8KB, 16KB, or 32KB
Number of TCM blocks
0, or auto-configures
a
to 1, or 2
a. Number of TCM blocks depends only on the size of the
TCM RAM.
Table 1-5 ARM1176JZF-S processor default configurations
Feature Default value
IEM support No
Cache way size 4KB
Number of cache ways 4
TCM block size 8KB
Number of TCM blocks 2

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English