Debug Test Access Port
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-42
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14.10 Monitor debug-mode debugging
If DSCR[15:14] b10 selecting Monitor debug-mode, then the processor takes an exception,
rather than halting, when a software debug event occurs. See Halting debug-mode debugging on
page 13-50 for details. When the exception is taken, the handler uses the DCC to transmit status
information to, and receive commands from the host using a DBGTAP debugger. Monitor
debug-mode is essential in real-time systems when the core cannot be halted to collect
information.
14.10.1 Receiving data from the core
SCAN_N 5 ; select DTR
INTEST
FOREACH Data2Read
LOOP
DATA 0x00000000 Valid readData
UNTIL Valid==1 ; wait until instruction ends
Save value in readData
END
14.10.2 Sending data to the core
SCAN_N 5 ; select DTR
EXTEST
FOREACH Data2Write
LOOP
DATA Data2Write nRetry
UNTIL nRetry==1 ; wait until instruction ends
END
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