To Next Page

To Previous Page

VFP Programmer’s Model

ID012310 Non-Confidential, Unrestricted Access

Table 20-6 lists the FPSCR bit fields.

Table 20-6 Encoding of the Floating-Point Status and Control Register

Bits Name Meaning

[31] N Set if comparison produces a less than result

[30] Z Set if comparison produces an equal result

[29] C Set if comparison produces an equal, greater than, or unordered result

[28] V Set if comparison produces an unordered result

[27:26] - Should Be Zero

[25] DN Default NaN mode enable bit:

1 = default NaN mode enabled

0 = default NaN mode disabled

[24] FZ Flush-to-zero mode enable bit:

1 = flush-to-zero mode enabled

0 = flush-to-zero mode disabled

[23:22] Rmode Rounding mode control field:

b00 = Round to nearest (RN) mode

b01 = Round towards plus infinity (RP) mode

b10 = Round towards minus infinity (RM) mode

b11 = Round towards zero (RZ) mode

[21:20] Stride See Vector length and stride control on page 20-16

[19] - Should Be Zero

[18:16] LEN See Vector length and stride control on page 20-16

[15] IDE Input Subnormal exception trap enable bit

[14:13] - Should Be Zero

[12] IXE Inexact exception trap enable bit

[11] UFE Underflow exception trap enable bit

[10] OFE Overflow exception trap enable bit

[9] DZE Division by Zero exception trap enable bit

[8] IOE Invalid Operation exception trap enable bit

[7] IDC Input Subnormal cumulative exception flag

[6:5] - Should Be Zero

[4] IXC Inexact cumulative exception flag

[3] UFC Underflow cumulative exception flag

[2] OFC Overflow cumulative exception flag

[1] DZC Division by Zero cumulative exception flag

[0] IOC Invalid Operation cumulative exception flag

ARM ARM1176JZF-S User Manual

Questions and Answers: