System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-55
ID012310 Non-Confidential, Unrestricted Access
Table 3-50 lists the results of attempted access for each mode.
To use the Secure Debug Enable Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c1
• CRm set to c1
• Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c1, c1, 1 ; Read Secure Debug Enable Register
MCR p15, 0, <Rd>, c1, c1, 1 ; Write Secure Debug Enable Register
3.2.12 c1, Non-Secure Access Control Register
The purpose of the Non-Secure Access Control Register is to define the Non-secure access
permission for:
• coprocessors
• cache lockdown registers
• TLB lockdown registers
• internal DMA.
Note
This register has no effect on Non-secure access permissions for the debug control coprocessor,
CP14, or the system control coprocessor, CP15.
The Non-Secure Access Control Register is:
•in CP15 c1
• a 32 bit register:
— read/write in the Secure world
— read only in the Non-secure world
• only accessible in privileged modes.
Figure 3-31 on page 3-56 shows the arrangement of bits in the register.
Table 3-50 Results of access to the Coprocessor Access Control Register
Secure Privileged
Non-secure Privileged User
Read Write
Data Data Undefined exception Undefined exception
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