System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-59
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• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c2, c0, 0 ; Read Translation Table Base Register 0
MCR p15, 0, <Rd>, c2, c0, 0 ; Write Translation Table Base Register 0
Note
The ARM1176JZF-S processor cannot page table walk from level one cache. Therefore, if C is
set to 1, to ensure coherency, you must either store page tables in Inner write-through memory
or, if in Inner write-back, you must clean the appropriate cache entries after modification so that
the mechanism for the hardware page table walks sees them.
3.2.14 c2, Translation Table Base Register 1
The purpose of the Translation Table Base Register 1 is to hold the physical address of the
first-level table. The expected use of the Translation Table Base Register 1 is for OS and I/O
addresses.
Table 3-55 lists the purposes of the individual bits in the Translation Table Base Register 1.
The Translation Table Base Register 1 is:
•in CP15 c2
• a 32 bit read/write register banked for Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-33 shows the bit arrangement for the Translation Table Base Register 1.
Figure 3-33 Translation Table Base Register 1 format
Table 3-55 lists how the bit values correspond with the Translation Table Base Register 1
functions.
Translation table base 1
31 14 13
SCP
0
UNP/SBZ
1
2
3
RGN
4
5
Table 3-55 Translation Table Base Register 1 bit functions
Bits Field name Function
[31:14] Translation table base 1 Holds the translation table base address, the physical address of the first level
translation table. The reset value is 0.
[13:5] - UNP/SBZ.
[4:3] RGN Indicates the Outer cacheable attributes for page table walking:
b00 = Outer Noncacheable, reset value
b01 = Write-back, Write Allocate
b10 = Write-through, No Allocate on Write
b11 = Write-back, No Allocate on Write.
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