System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-5
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3.1.2 System control and configuration
The purpose of the system control and configuration registers is to provide overall management
of:
• TrustZone behavior
• memory functionality
• interrupt behavior
• exception handling
• program flow prediction
• coprocessor access rights for CP0-CP13.
The system control and configuration registers also provide the processor ID.
The system control and configuration registers consist of three 32-bit read only registers and
eight 32-bit read/write registers. Figure 3-1 shows the arrangement of registers in this functional
group.
Figure 3-1 System control and configuration registers
To use the system control and configuration registers you read or write individual registers that
make up the group, see Use of the system control coprocessor on page 3-12.
System validation Secure User and Non-secure Access
Validation Control
c15, Secure User and Non-secure Access Validation Control
Register on page 3-132
System Validation Counter c15, System Validation Counter Register on page 3-140
System Validation Operations c15, System Validation Operations Register on page 3-142
System Validation Cache Size Mask c15, System Validation Cache Size Mask Register on
page 3-145
a. Returns device ID code.
Table 3-1 System control coprocessor register functions (continued)
Function Register/operation Reference to description
CRn
c1
Coprocessor Access Control Register
Auxiliary Control Register
Control Register
1
2
0
c00
Opcode_2CRmOpcode_1
c0
ID Code Register
0c00
Write-only Accessible in User modeRead-only Read/write
2
Secure Configuration Register
Non-secure Access Control Register
CPUID Registers
CPUID Registers
CPUID Registers
CPUID Registers
CPUID Registers
CPUID Registers
CPUID Registers
Secure Debug Enable Register
1
c12
Monitor Vector Base Address Register
Non-secure or Secure Vector Base Address Register
1
0c00
Interrupt Status Register
2
c1
{0-7}
c1
{0-7}
{0-7}
{0-7}
{0-7}
{0-7}
{0-7}
c2
c3
c4
c5
c6
c7
0
c1