Signal Descriptions
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A.5 AXI interface signals
The AXI interface ports operate using standard AXI signals, described in the following sections:
• Instruction read port signals
• Data port signals on page A-8
• Peripheral port signals on page A-9
• DMA port signals on page A-10.
Note
• All the outputs listed in this section have their reset values during Standby.
• Full descriptions of the AXI interface signals are given in the AMBA
®
AXI Protocol V1.0
Specification. This section only summarizes how the AXI interfaces are implemented on
this processor.
The AXI signal names have a one or two-letter suffix that indicate the port, as shown in
Table A-5.
A.5.1 Instruction read port signals
The instruction read port is a 64-bit wide read-only AXI port. The standard AXI read channel
signal names are suffixed with I, and the implementation details of the port are:
• ARID[3:0] and RID[3:0] signals are not implemented
• the read data bus is implemented as RDATAI[63:0]
• the ARSIDEBANDI[4:0] output is implemented to indicate shared and inner cacheable
accesses.
Table A-6 on page A-8 gives more information about the instruction read port AXI
implementation. See the AMBA
®
AXI Protocol V1.0 Specification for details of the other
signals on this port.
Table A-5 Port signal name suffixes
Port Suffix Comment
Instruction fetch I Read-only
Data read/write RW Read/write
Peripheral P Read/write
DMA D Read/write
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