Debug Test Access Port
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-29
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14.8 Debug sequences
This section describes how to debug a program running on the processor using a DBGTAP
debugger device such as RealView ICE. In Halting debug-mode, the processor stops when a
debug event occurs enabling the DBGTAP debugger to do the following:
1. Perform a Data Synchronization Barrier operation to ensure imprecise data aborts are
recognized and DSCR[19] is set.
2. Determine and modify the current state of the processor and memory.
3. Set up breakpoints, watchpoints, and vector traps.
4. Restart the processor.
You enable this mode by setting CP14 debug DSCR[14] bit. Only the DBGTAP debugger can
do this. From here, it is assumed that the debug unit is in Halting debug-mode. Monitor
debug-mode debugging on page 14-42 describes the monitor debug-mode debugging.
14.8.1 Debug macros
The debug code sequences in this section are written using a fixed set of macros. The mapping
of each macro into a debug scan chain sequence is given in this section.
Scan_N <n>
Select scan chain register number <n>:
1. Scan the Scan_N instruction into the IR.
2. Scan the number <n> into the DR.
INTEST
1. Scan the INTEST instruction into the IR.
EXTEST
1. Scan the EXTEST instruction into the IR.
ITRsel
1. Scan the ITRsel instruction into the IR.
Restart
1. Scan the Restart instruction into the IR.
2. Go to the DBGTAP controller Run-Test/Idle state so that the processor exits Debug state.
INST <instr> [stateout]
Go through Capture-DR, go to Shift-DR, scan in an ARM instruction to be read and executed
by the core and scan out the Ready flag, go through Update-DR. The ITR, scan chain 4, and
EXTEST must be selected when using this macro.
1. Scan in:
• Any value for the InstCompl flag. This bit is read-only.
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