ARM ARM1176JZF-S - Figure 3-19 Memory Model Feature Register 2 Format; Table 3-24 Memory Model Feature Register 2 Bit Functions

System Control Coprocessor
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Figure 3-19 Memory Model Feature Register 2 format
Table 3-24 lists how the bit values correspond with the Memory Model Feature Register 2
functions.
- - - - - - -
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
-
Table 3-24 Memory Model Feature Register 2 bit functions
Bits Field name Function
[31:28] - Indicates support for a Hardware access flag.
0x0 , no support in ARM1176JZF-S processors.
[27:24] - Indicates support for Wait For Interrupt stalling.
0x1 , ARM1176JZF-S processors support Wait For Interrupt.
[23:20] - Indicates support for memory barrier operations.
0x2 , ARM1176JZF-S processors support:
• Data Synchronization Barrier
• Prefetch Flush
• Data Memory Barrier.
[19:16] - Indicates support for TLB maintenance operations, unified architecture.
0x2 , ARM1176JZF-S processors support:
• invalidate all entries
• invalidate TLB entry by MVA
• invalidate TLB entries by ASID match.
[15:12] - Indicates support for TLB maintenance operations, Harvard architecture.
0x2 , ARM1176JZF-S processors support:
• invalidate instruction and data TLB, all entries
• invalidate instruction TLB, all entries
• invalidate data TLB, all entries
• invalidate instruction TLB by MVA
• invalidate data TLB by MVA
• invalidate instruction and data TLB entries by ASID match
• invalidate instruction TLB entries by ASID match
• invalidate data TLB entries by ASID match.
[11:8] - Indicates support for cache maintenance range operations, Harvard architecture.
0x1 , ARM1176JZF-S processors support:
• invalidate data cache range by VA
• invalidate instruction cache range by VA
• clean data cache range by VA
• clean and invalidate data cache range by VA.
[7:4] - Indicates support for background prefetch cache range operations, Harvard architecture.
0x0 , no support in ARM1176JZF-S processors.
[3:0] - Indicates support for foreground prefetch cache range operations, Harvard architecture.
0x0 , no support in ARM1176JZF-S processors.