Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-11
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AxSIZE[2:0]
This signal indicates the size of each transfer. Table 8-3 shows the supported transfer sizes.
AxBURST[1:0]
The AxBURST[1:0] signals indicate a fixed, incrementing or wrapping burst. Table 8-4 shows
the burst types that the ARM1176JZF-S processor supports.
The processor uses:
• Wrapping bursts for some cache line fills
• Incrementing bursts for accesses to noncacheable memory, including instruction fetches.
AxLOCK[1:0]
The AxLOCK[1:0] signal indicates the lock type of access. The processor supports all locked
type accesses. The instruction port only generates Normal access types. The DMA port only
generates Normal access types. The Data Read/Write port generates all access types, Normal,
exclusive and locked access.
Table 8-5 shows the values of AxLOCK that the processor supports.
Table 8-3 AxSIZE[2:0] encoding
AxSIZE[2:0] Bytes in transfer
b000 1
b001 2
b010 4
b011 8
Table 8-4 AxBURST[1:0] encoding
AxBURST[2:0] Burst type Description
b00 Fixed Fixed address burst
b01 Incr Incrementing address burst
b10 Wrap Incrementing address burst that wraps to a lower address at the wrap boundary
Table 8-5 AxLOCK[1:0] encoding
AxLOCK[1:0] Description
b00 Normal access
b01 Exclusive access
b10 Locked access
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