Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-9
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• Registers
• Modes and exceptions
• Thumb instruction set on page 1-10
• DSP instructions on page 1-10
• Media extensions on page 1-10
• Datapath on page 1-10
• Branch prediction on page 1-11
• Return stack on page 1-11.
Instruction set categories
The main instruction set categories are:
• branch instructions
• data processing instructions
• status register transfer instructions
• load and store instructions
• coprocessor instructions.
• exception-generating instructions.
Note
Only load, store, and swap instructions can access data from memory.
Conditional execution
The processor conditionally executes nearly all ARM instructions. You can decide if the
condition code flags, Negative, Zero, Carry, and Overflow, are updated according to their result.
Registers
The ARM1176JZF-S core contains:
• 33 general-purpose 32-bit registers
• 7 dedicated 32-bit registers.
Note
At any one time, 16 general-purpose registers are visible. The remainder are banked registers
used to speed up exception processing.
Modes and exceptions
The core provides a set of operating and exception modes, to support systems combining
complex operating systems, user applications, and real-time demands. There are eight operating
modes, six of them are exception processing modes:
•User
• Supervisor
• fast interrupt
• normal interrupt
•abort
•system
• Undefined
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