Memory Management Unit
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-6
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bit in the MMU for regions that are Cacheable as making the accesses Noncacheable. This
ensures memory coherency without incurring the cost of dedicated cache coherency hardware.
Behavior with MMU disabled on page 6-9 describes the behavior of the memory system when
the MMU is disabled.
6.2.5 Supersections
Supersections are defined using a first level descriptor in the page tables, similar to the way a
Section is defined. Because each first level page table entry covers a 1MB region of virtual
memory, the 16MB supersections require that 16 identical copies of the first level descriptor of
the supersection exist in the first level page table.
Every supersection is defined to have its Domain as 0.
Supersections can be specified regardless of whether subpages are enabled or not, as controlled
by the CP15 Control Register XP bit, bit [23]. This bit is duplicated as Secure and Non-secure,
so that supersections can be enabled or disabled separately in each world. Figure 6-6 on
page 6-38 and Figure 6-9 on page 6-41 show the page table formats of supersections.
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