ARM ARM1176JZF-S - About the Processor VIC Port; Table 12-1 VIC Port Signals; Figure 12-1 Connection of a VIC to the Processor

Vectored Interrupt Controller Port
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12.2 About the processor VIC port
Figure 12-1 shows the VIC port and the Peripheral Interface connecting a PL192 VIC and the
processor.
Figure 12-1 Connection of a VIC to the processor
Note
Do not be confused by the naming of the IRQADDRVSYNCEN and nVICSYNCEN signals.
Although one is active HIGH and the other is active LOW they are connected to a common
external synchronization disable signal. See the signal descriptions in Table 12-1 for more
information.
The VIC port enables the processor to read the vector address as part of the IRQ interrupt entry.
That is, the processor takes a vector address from this interface instead of using the legacy
0x00000018 or 0xFFFF0018 .The VIC port does not support the reading of FIQ vector addresses.
The interrupt interface is designed to handle interrupts asserted by a controller that is clocked
either synchronously or asynchronously to the processor clock. This capability ensures that the
controller can be used in systems that have either a synchronous or asynchronous interface
between the core clock and the AXI clock.
The VIC port consists of the signals that Table 12-1 lists.
IRQACK is driven by the processor to indicate to an external VIC that the processor wants to
read the IRQADDR input.
nFIQ
nIRQ
IRQADDRV
IRQADDR[31:2] VICVECTADDROUT[31:2]
VICIRQADDRV
VICIRQACK
nVICIRQ
nVICFIQ
VIC
Processor
nVICSYNCEN
IRQACK
IRQADDRVSYNCEN
INTSYNCEN
0
VICVECTADDRIN[31:0]
VICINTSOURCE[(N-1):0]
nVICFIQIN
nVICIRQIN
Table 12-1 VIC port signals
Signal name Direction Description
nFIQ Input Active LOW fast interrupt request signal
nIRQ Input Active LOW normal interrupt request signal
INTSYNCEN Input If this signal is asserted HIGH, the internal nFIQ and nIRQ synchronizers are
bypassed and the interface is synchronous
IRQADDRVSYNCEN Input If this signal is asserted HIGH, the internal IRQADDRV synchronizer is
bypassed and the interface is synchronous
IRQACK Output Active HIGH IRQ acknowledge
IRQADDRV Input Active HIGH valid signal for the IRQ interrupt vector address below
IRQADDR[31:2] Input IRQ interrupt vector address. IRQADDR[31:2] holds the address of the first
ARM state instruction in the IRQ handler