VFP Exception Handling
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-2
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22.1 About exception processing
The VFP11 coprocessor handles exceptions, other than inexact exceptions, imprecisely with
respect to both the state of the ARM11 processor and the state of the VFP11 coprocessor. It
detects an exceptional instruction after the instruction passes the point for exception handling in
the ARM11 processor. It then enters the exceptional state and signals the presence of an
exception by refusing to accept a subsequent VFP instruction. The instruction that triggers
exception handling bounces to the ARM11 processor. The bounced instruction is not necessarily
the instruction immediately following the exceptional instruction. Depending on sequence of
instructions that follow, the bounce can occur several instructions later.
The VFP11 coprocessor can generate exceptions only on arithmetic operations. Data transfer
operations between the ARM11 processor and the VFP11 coprocessor, and instructions that
copy data between VFP11 registers, FCPY, FABS, and FNEG, cannot produce exceptions.
In full-compliance mode the VFP11 hardware and support code together process exceptions
according to the IEEE 754 standard. VFP11 exception processing includes calling user trap
handlers with intermediate operands specified by the IEEE 754 standard. In RunFast mode, the
VFP11 coprocessor generates the default, or trap disabled, value when an overflow, invalid
operation, division by zero, or inexact condition occurs. RunFast mode does not provide for user
trap handlers.
For descriptions of each of the exception flags and their bounce characteristics, see the sections
Input Subnormal exception on page 22-12 to Arithmetic exceptions on page 22-20.
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