Unaligned and Mixed-endian Data Access Support
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-8
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Figure 4-5 Load unsigned halfword, big-endian
If strict alignment fault checking is enabled and Address bit 0 is not zero, then a Data Abort is
generated and the MMU returns a Misaligned fault in the Fault Status Register.
4.3.6 Load signed halfword, little-endian
The addressed byte-pair is loaded from memory into the low 16-bits of the general-purpose
register, so that the least-significant addressed byte in memory appears in bits [7:0] of the ARM
register and the upper 16 bits are sign-extended from bit 15, as Figure 4-6 shows.
Figure 4-6 Load signed halfword, little-endian
In Figure 4-6, se1 means bit 15, b1 bit [7], sign extended.
If strict alignment fault checking is enabled and Address bit 0 is not zero, then a Data Abort is
generated and the MMU returns a Misaligned fault in the Fault Status Register.
4.3.7 Load signed halfword, big-endian
The addressed byte-pair is loaded from memory into the low 16-bits of the general-purpose
register, so that the most significant addressed byte in memory appears in bits [15:8] of the ARM
register and bits [31:16] replicate the sign bit in bit 15, as Figure 4-7 on page 4-9 shows.
B1
B0
Memory Register
31 23 15 7 0
Address
A[31:0]
70
0 0 B0 B1
+1 lsbyte
msbyte
b1
b0
Memory Register
31 23 15 7 0
Address
A[31:0]
70
se1 se1 b1 b0
+1 msbyte
lsbyte
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