Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-32
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8.5.31 Cacheable Write-Through or Noncacheable STM8
Table 8-60 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for an STM8 to word 0 over the Data Read/Write Interface.
An STM8 to words 1 to 7 is split into two operations as shown in Table 8-61.
8.5.32 Cacheable Write-Through or Noncacheable STM9
An STM9 over the Data Read/Write Interface is split into two operations as shown in
Table 8-62.
Table 8-59 Cacheable Write-Through or Noncacheable STM7 to word 2, 3, 4, 5, 6 or 7
Address[4:0] Operations
0x08
, word 2 STM6 to
0x08
+ STR to
0x00
0x0C
, word 3 STM5 to
0x0C
+ STM2 to
0x00
0x10
, word 4 STM4 to
0x10
+ STM3 to
0x00
0x14
, word 5 STM3 to
0x14
+ STM4 to
0x00
0x18
, word 6 STM2 to
0x18
+ STM5 to
0x00
0x1C
, word 7 STR to
0x1C
+ STM6 to
0x00
Table 8-60 Cacheable Write-Through or Noncacheable STM8 to word 0
Address[4:0]
AWADDRR
W
AWBURSTR
W
AWSIZERW AWLENRW First WSTRBRW
0x00
, word 0
0x00
Incr 64-bit 4 data transfers b1111 1111
Table 8-61 Cacheable Write-Through or Noncacheable STM8 to word 1, 2, 3, 4, 5, 6, or 7
Address[4:0] Operations
0x04
, word 1 STM7 to
0x04
+ STR to
0x00
0x08
, word 2 STM6 to
0x08
+ STM2 to
0x00
0x0C
, word 3 STM5 to
0x0C
+ STM3 to
0x00
0x10
, word 4 STM4 to
0x10
+ STM4 to
0x00
0x14
, word 5 STM3 to
0x14
+ STM5 to
0x00
0x18
, word 6 STM2 to
0x18
+ STM6 to
0x00
0x1C
, word 7 STR to
0x1C
+ STM7 to
0x00
Table 8-62 Cacheable Write-Through or Noncacheable STM9
Address[4:0] Operations
0x00
, word 0 STM8 to
0x00
+ STR to
0x00
0x04
, word 1 STM7 to
0x04
+ STM2 to
0x00
0x08
, word 2 STM6 to
0x08
+ STM3 to
0x00
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