Signal Descriptions
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• the read data bus is implemented as RDATAP[31:0]
• the ARSIDEBANDP[4:0] output and AWSIDEBANDP[4:0] output signals are
implemented to indicate shared and inner cacheable accesses. These signals have fixed
values.
Table A-8 gives more information about the peripheral port AXI implementation. See the
AMBA
®
AXI Protocol V1.0 Specification for details of the other signals on this port.
A.5.4 DMA port signals
The DMA port is a 64-bit wide read/write AXI port. The standard AXI read channel, write
channel, and write response channel signal names are suffixed with D, and the implementation
details of the port are:
• AWID[3:0], WID[3:0], BID[3:0], ARID[3:0], and RID[3:0] signals are not
implemented
• the write data bus is implemented as WDATAD[63:0], and therefore the write strobe
signal is implemented as WSTRBD[7:0]
Table A-8 Peripheral port AXI signal implementation
Name Direction Type Description
AWSIZEP[2:0] Output Write Write burst size:
b000, 8-bit transfers
b001, 16-bit transfers
b010, 32-bit transfers, maximum for the peripheral port.
AWBURSTP[1:0] Output Write Write burst type, always set to b01, INCR, Incrementing burst.
AWLOCKP[1:0] Output Write Write lock type, always set to b00, Normal access.
AWCACHEP[3:0] Output Write Cache type giving additional information about cacheable
characteristics for write accesses. Always set to 0x1.
ARLENP[3:0] Output Read Burst length that gives the exact number of transfer:
b0000, 1 data transfer
b0001, 2 data transfers.
ARSIZEP[2:0] Output Read Burst size:
b000, 8-bit transfer
b001, 16-bit transfer
b010, 32-bit transfer.
ARBURSTP[1:0] Output Read Read burst type, always set to b01, INCR, Incrementing burst.
ARLOCKP[1:0] Output Read Lock type:
b00, normal access
b10, locked transfer.
ARCACHEP[3:0] Output Read Cache type giving additional information about cacheable
characteristics. Always set to 0x1.
ARSIDEBANDP[4:0] Output Read Indicates read accesses to shared and inner cacheable memory.
Always set to 0x2.
AWSIDEBANDP[4:0] Output Write Indicates write accesses to shared and inner cacheable memory.
Always set to 0x2.
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