ARM ARM1176JZF-S User Manual

Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-14
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8.4 Instruction Fetch Interface transfers
The tables in this section describe the AXI interface behavior for instruction side fetches to
either Cacheable or Noncacheable regions of memory for the following interface signals:
• ARBURSTI[1:0]
• ARLENI[3:0]
• ARADDRI[31:0]
• ARSIZEI[2:0].
See the AMBA AXI Protocol Specification for details of the other AXI signals.
8.4.1 Cacheable fetches
Table 8-10 shows the values of ARADDRI, ARBURSTI, ARSIZEI, and ARLENI for
Cacheable fetches.
8.4.2 Noncacheable fetches
Table 8-11 shows the values of ARADDRI, ARBURSTI, ARSIZEI, and ARLENI for
Noncacheable fetches.
Table 8-10 AXI signals for Cacheable fetches
Address[4:0] ARADDRI ARBURSTI ARSIZEI ARLENI
0x00 , word 0 0x00 Incr 64-bit 4 data transfers
0x04 , word 1 0x00 Incr 64-bit 4 data transfers
0x08 , word 2 0x08 Wrap 64-bit 4 data transfers
0x0C , word 3 0x08 Wrap 64-bit 4 data transfers
0x10 , word 4 0x10 Wrap 64-bit 4 data transfers
0x14 , word 5 0x10 Wrap 64-bit 4 data transfers
0x18 , word 6 0x18 Wrap 64-bit 4 data transfers
0x1C , word 7 0x18 Wrap 64-bit 4 data transfers
Table 8-11 AXI signals for Noncacheable fetches
Address[4:0] ARADDRI ARBURSTI ARSIZEI ARLENI
0x00 , word 0 0x00 Incr 64-bit 4 data transfers
0x04 , word 1 0x04 Incr 64-bit 4 data transfers
0x08 , word 2 0x08 Incr 64-bit 3 data transfers
0x0C , word 3 0x0C Incr 64-bit 3 data transfers
0x10 , word 4 0x10 Incr 64-bit 2 data transfers
0x14 , word 5 0x14 Incr 64-bit 2 data transfers
0x18 , word 6 0x18 Incr 64-bit 1 data transfer
0x1C , word 7 0x1C Incr 64-bit 1 data transfer

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English