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Memory Management Unit

ID012310 Non-Confidential, Unrestricted Access

Table 6-6 lists how the memory type, the value of the S bit in the page table attributes, and the

primary remap region register determine how the pages can be shared.

Table 6-7 lists the encoding used for each region in the PRRR register, bits [15:0].

Table 6-8 lists the encoding used for each Inner or Outer Cacheable attribute in the NMRR

When the MMU is off the remapping takes place according to the settings in PRRR[1:0], and

PRRR[19],PRRR[17], NMRR[1:0], and NMRR[17:16] as appropriate.

In this case, the S bit is treated as if it is 1 prior to remapping. This behavior takes place

regardless of whether or not the instruction cache is enabled.

Note

• The reset value for each field of the PRRR and NMRR makes the MMU behave as if no

remapping occurs, that is Strongly Ordered regions are remapped as Strongly Ordered and

so on.

• For security reasons, the NS Attribute bit has no remap capability.

Table 6-6 Values that remap the shareable attribute

Memory Type

Shareable attribute when:

S=0 S=1

Strongly Ordered Shareable Shareable

Device PRRR[16] PRRR[17]

Normal PRRR[18] PRRR[19]

Table 6-7 Primary region type encoding

Region Encoding

Strongly Ordered b00

Device b01

Normal Memory b10

Unpredictable, normal memory for ARM1176JZF-S b11

Table 6-8 Inner and outer region remap encoding

Inner or Outer Region Encoding

Non-Cacheable b00

WriteBack, WriteAllocate b01

WriteThrough, Non-Write Allocate b10

WriteBack, Non-WriteAllocate b11

ARM ARM1176JZF-S User Manual

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