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VFP Instruction Execution

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Table 21-9 lists the VFP11 pipeline stages of Example 21-7 on page 21-14.

21.7.5 Short vector CDP-load multiple WAR hazard example

In Example 21-8, the load multiple FLDMS creates a WAR hazard to the source registers of the

FMULS. The LEN field contains b011, selecting a vector length of four iterations, and the

STRIDE field contains b00, selecting a vector stride of one. The VFP11 coprocessor stalls the

FLDMS until the FMULS clears the scoreboard locks for all the source registers, S16-S19 and

S24-S27.

Example 21-8 Short vector FMULS-FLDMS WAR hazard

FMULS S8, S16, S24

FLDMS [R2], {S16-S27}

Table 21-10 lists the VFP11 pipeline stages for the first iteration of Example 21-8.

Table 21-9 FMULS-FADDS RAW hazard

Instruction cycle number

Instruction1234567891011

FMULS DI E1E2E3E4E5E6E7W -

FADDS - D I IIIIIIIEI

Table 21-10 Short vector FMULS-FLDMS WAR hazard

Instruction cycle number

Instruction123456789 10111213141516

FMULS DI E1E1E1E1E2E3E4 E5 E6E7W - - -

FLDMS -DIIIIIEM1M2WWWWWW

ARM ARM1176JZF-S User Manual

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