Cycle Timings and Interlock Behavior
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-4
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Finally, some instructions do not require a register until their second execution cycle. If a
register is not required until the ALU, MAC1, or Dc1 stage for the second execution cycle, then
a cycle can be subtracted from the result latency for the instruction producing the required
register. If a register is not required until this later point, it is specified as a Late Reg. The
following sequence where R1 is a Late Reg takes four cycles:
LDR R1, [R2] ;Result latency three minus one
ADD R3, R3, R1, R4 LSL#5 ;minus one because Register R1 is a Late Reg
;This ADD is a two issue cycle instruction
16.1.3 Conditional instructions
Most instructions execute in one or two cycles. If these instructions fail their condition codes
then they take one and two cycles respectively.
Multiplies, MSR, and some CP14 and CP15 coprocessor instructions are the only instructions
that require more than two cycles to execute. If one of these instructions fails its condition codes,
then it takes a variable number of cycles to execute. The number of cycles is dependent on:
• the length of the operation
• the number of cycles between the setting of the flags and the start of the dependent
instruction.
The worst-case number of cycles for a condition code failing multicycle instruction is five.
The following algorithm describes the number of cycles taken for multi-cycle instructions that
condition-code fail:
Min(NonFailingCycleCount, Max(5 - FlagCycleDistance, 3))
Where:
Max (a,b) Returns the maximum of the two values a,b.
Min (a,b) Returns the minimum of the two values a,b.
NonFailingCycleCount
Is the number of cycles that the failing instruction would have taken had it
passed.
FlagCycDistance Is the number of cycles between the instruction that sets the flags and the
conditional instruction, including interlocking cycles. For example:
• The following sequence has a FlagCycleDistance of 0 because the
instructions are back-to-back with no interlocks:
ADDS R1, R2, R3
MULEQ R4, R5, R6
• The following sequence has a FlagCycleDistance of one:
ADDS R1, R2, R3
MOV R0, R0
MULEQ R4, R5, R6
16.1.4 Opposite condition code checks
If instruction A and instruction B both write the same register the pipeline must ensure that the
register is written in the correct order. Therefore, interlocks might be required to correctly
resolve this pipeline hazard.
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