Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-57
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PC = 0xFFFF001C
else
PC = Non_Secure_Base_Address + 0x0000001C
Secure Monitor Call Exception
On a SMC:
If (UserMode) /* undefined instruction */
R14_und = address of the next instruction after the SMC instruction
SPSR_und = CPSR
CPSR [4:0] = 0b11011 /* Enter undefined instruction mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [7] = 1 /* Disable interrupts */
CPSR [9] = Secure EE-bit /* store value of secure Control Reg[25] */
CPSR[24] = 0 /* Clear J bit */
If high vectors configured then
PC = 0xFFFF0004
else
PC = Secure_Base_Address + 0x00000004
else
R14_mon = address of the next instruction after the SMC instruction
SPSR_mon = CPSR
CPSR [4:0] = 0b10110 /* Enter Secure Monitor mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [6] = 1 /* Disable fast interrupts */
CPSR [7] = 1 /* Disable interrupts */
CPSR [8] = 1 /* Disable imprecise aborts */
CPSR [9] = Secure EE-bit /* store value of secure Control Reg[25] */
CPSR[24] = 0 /* Clear J bit */
PC = Monitor_Base_Address + 0x00000008 /* SMC vectored to the */
/*conventional SVC vector */
2.12.17 Exception priorities
When multiple exceptions arise at the same time, a fixed priority system determines the order
that they are handled. Table 2-9 lists the order of exception priorities.
Some exceptions cannot occur together:
• The BKPT, undefined instruction, SMC, and SVC exceptions are mutually exclusive.
Each corresponds to a particular, non-overlapping, decoding of the current instruction.
Table 2-9 Exception priorities
Priority Exception
Highest 1 Reset
2 Precise Data Abort
3FIQ
4IRQ
5 Prefetch Abort
6 Imprecise Data Abort
Lowest 7 BKPT
Undefined Instruction
SVC
SMC
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