ARM ARM1176JZF-S User Manual

Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-41
ID012310 Non-Confidential, Unrestricted Access
Table 1-9 summarizes addressing mode 2P, post-indexed only.
Pre-indexed offset -
Immediate offset
[<Rn>], #+/<immed_12>
Zero offset [<Rn>]
Register offset [<Rn>, +/-<Rm>] !
Scaled register offset
[<Rn>, +/-<Rm>, LSL #<immed_5>] !
[<Rn>, +/-<Rm>, LSR #<immed_5>] !
[<Rn>, +/-<Rm>, ASR #<immed_5>] !
[<Rn>, +/-<Rm>, ROR #<immed_5>] !
[<Rn>, +/-<Rm>, RRX] !
Post-indexed offset -
Immediate [<Rn>], #+/-<immed_12>
Zero offset [<Rn>]
Register offset [<Rn>], +/-<Rm>
Scaled register offset [<Rn>], +/-<Rm>, LSL #<immed_5>
[<Rn>], +/-<Rm>, LSR #<immed_5>
[<Rn>], +/-<Rm>, ASR #<immed_5>
[<Rn>], +/-<Rm>, ROR #<immed_5>
[<Rn>], +/-<Rm>, RRX
Table 1-9 Addressing mode 2P, post-indexed only
Addressing mode Assembler
Post-indexed offset -
Immediate offset [<Rn>], #+/-<immed_12>
Zero offset [<Rn>]
Register offset [<Rn>], +/-<Rm>
Scaled register offset [<Rn>], +/-<Rm>, LSL #<immed_5>
[<Rn>], +/-<Rm>, LSR #<immed_5>
[<Rn>], +/-<Rm>, ASR #<immed_5>
[<Rn>], +/-<Rm>, ROR #<immed_5>
[<Rn>], +/-<Rm>, RRX
Table 1-8 Addressing mode 2 (continued)
Addressing mode Assembler

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English