ARM ARM1176JZF-S - Page 66

Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-40
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Table 1-8 summarizes addressing mode 2.
Signed (high 16 x 16) +
(low 16 x 16), and set Q flag
SMUAD{cond} <Rd>, <Rm>, <Rs>
As SMUAD , but high x low,
low x high, and set Q flag
SMUADX{cond} <Rd>, <Rm>, <Rs>
Signed (high 16 x 16) -
(low 16 x 16)
SMUSD{cond} <Rd>, <Rm>, <Rs>
As SMUSD , but high x low,
low x high
SMUSDX{cond} <Rd>, <Rm>, <Rs>
Truncated high 16 (32 x 32) SMMUL{cond} <Rd>, <Rm>, <Rs>
Rounded high 16 (32 x 32) SMMULR{cond} <Rd>, <Rm>, <Rs>
Unsigned 32 x 32, + two 32, to 64 UMAAL{cond} <RdLo>, <RdHi>, <Rm>, <Rs>
Saturate, select,
and pack
Signed saturation at
bit position n
SSAT{cond} <Rd>, #<immed_5>, <Rm>{, <shift>}
Unsigned saturation at
bit position n
USAT{cond} <Rd>, #<immed_5>, <Rm>{, <shift>}
Two 16 signed saturation at
bit position n
SSAT16{cond} <Rd>, #<immed_4>, <Rm>
Two 16 unsigned saturation at
bit position n
USAT16{cond} <Rd>, #<immed_4>, <Rm>
Select bytes from Rn / Rm based
on GE flags
SEL{cond} <Rd>, <Rn>, <Rm>
Pack low 16/32, high 16/32 PKHBT{cond} <Rd>, <Rn>, <Rm>{, LSL #<immed_5>}
Pack high 16/32, low 16/32 PKHTB{cond} <Rd>, <Rn>, <Rm>{, ASR #<immed_5>}
Table 1-7 ARM instruction set summary (continued)
Operation Assembler
Table 1-8 Addressing mode 2
Addressing mode Assembler
Offset -
Immediate offset
[<Rn>, #+/<immed_12>]
Zero offset [<Rn>]
Register offset [<Rn>, +/-<Rm>]
Scaled register offset [<Rn>, +/-<Rm>, LSL #<immed_5>]
[<Rn>, +/-<Rm>, LSR #<immed_5>]
[<Rn>, +/-<Rm>, ASR #<immed_5>]
[<Rn>, +/-<Rm>, ROR #<immed_5>]
[<Rn>, +/-<Rm>, RRX]