ARM ARM1176JZF-S - 16.18 Thumb Instructions

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Cycle Timings and Interlock Behavior

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16.18 Thumb instructions

The cycle timing behavior for Thumb instructions follow the ARM equivalent instruction cycle

timing behavior.

Thumb BL instructions that are encoded as two Thumb instructions, can be dynamically

predicted. The predictions occurs on the second part of the BL pair, consequently a correct

prediction takes two cycles.

Main Page

Default Chapter2
- Change History2
- Table of Contents4
Chapter 1 Introduction28
- About the Processor28
- Extensions to Armv629
- Figure29
- Trustzone Security Extensions30
- ARM1176JZF-S Architecture with Jazelle Technology32
- Components of the Processor34
  - Figure 1-1 ARM1176JZF-S Processor Block Diagram34
  - Conditional Execution35
  - Figure37
- Table 1-2 Double-Precision VFP Operations46
- Table 1-3 Flush-To-Zero Mode46
- Power Management49
- Configurable Options51
- Table 1-4 Configurable Options51
- Table 1-5 ARM1176JZF-S Processor Default Configurations51
- Pipeline Stages52
- Figure 1-2 ARM1176JZF-S Pipeline Stages52
- Typical Pipeline Operations54
- Figure 1-3 Typical Operations in Pipeline Stages54
- Figure 1-4 Typical ALU Operation54
- Figure 1-5 Typical Multiply Operation55
- Figure 1-6 Progression of an LDR/STR Operation56
- Figure 1-7 Progression of an LDM/STM Operation56
- Figure 1-8 Progression of an LDR that Misses57
- ARM1176JZF-S Instruction Set Summary58
- Table 1-7 ARM Instruction Set Summary59
- Table64
- Table 1-8 Addressing Mode 267
- Table 1-9 Addressing Mode 2P, Post-Indexed Only67
- Addressing Mode 368
  - Addressing Mode 468
- Addressing Mode 568
- Table 1-13 Operand269
- Table 1-14 Fields69
- Table 1-15 Condition Codes69
- Table 1-16 Thumb Instruction Set Summary70
- Product Revisions73
Chapter 2 Programmer's Model75
- About the Programmer's Model75
- Secure World and Non-Secure World Operation with Trustzone76
- Figure 2-1 Secure and Non-Secure Worlds76
- Figure 2-2 Memory in the Secure and Non-Secure Worlds79
- Figure 2-3 Memory Partition in the Secure and Non-Secure Worlds80
- Figure81
- Table 2-1 Write Access Behavior for System Control Processor Registers82
- Table 2-2 Secure Monitor Bus Signals84
- Processor Operating States85
- Instruction Length86
- Data Types87
- Memory Formats88
- Figure 2-4 Big-Endian Addresses of Bytes Within Words88
- Figure 2-5 Little-Endian Addresses of Bytes Within Words88
- Addresses in a Processor System89
- Table 2-3 Address Types in the Processor System89
- Operating Modes90
- Table 2-4 Mode Structure90
- Registers91
- Figure91
- Table 2-5 Register Mode Identifiers92
- Figure92
- Figure 2-6 Register Organization in ARM State93
- Figure 2-7 Processor Core Register Set Showing Banked Registers94
- Figure 2-8 Register Organization in Thumb State95
- Figure 2-9 ARM State and Thumb State Registers Relationship96
- The Program Status Registers97
- Figure 2-10 Program Status Register97
- Table 2-6 GE[3:0] Settings99
- Table 2-7 PSR Mode Bit Values101
- Additional Instructions103
- Copyright © 2004-2009 ARM Limited. All Rights Reserved103
- Figure 2-11 LDREXB Instruction103
- Figure 2-12 STREXB Instructions103
- Figure 2-13 LDREXH Instruction104
- Figure 2-14 STREXH Instruction105
- Figure 2-15 LDREXD Instruction106
- Figure 2-16 STREXD Instruction106
- Figure 2-17 CLREX Instruction107
- Figure 2-18 NOP-Compatible Hint Instruction107
- Exceptions109
- Table 2-8 Exception Entry and Exit110
- Exception Vectors121
- Table 2-9 Exception Priorities130
- Figure130
- Software Considerations132
Chapter 3 System Control Coprocessor133
- About the System Control Coprocessor134
- Table 3-1 System Control Coprocessor Register Functions135
- Figure 3-1 System Control and Configuration Registers137
- Figure 3-2 MMU Control and Configuration Registers139
- Figure 3-3 Cache Control and Configuration Registers140
- Figure 3-4 TCM Control and Configuration Registers140
- Figure 3-5 Cache Master Valid Registers141
- Figure 3-6 DMA Control and Configuration Registers141
- Figure 3-7 System Performance Monitor Registers142
- Figure 3-8 System Validation Registers143
- Figure 3-9 CP15 MRC and MCR Bit Pattern144
- System Control Processor Registers145
  - Table 3-2 Summary of CP15 Registers and Operations146
  - Table 3-3 Summary of CP15 MCRR Operations151
  - Figure 3-10 Main ID Register Format152
  - Table 3-4 Main ID Register Bit Functions152
  - Table 3-5 Results of Access to the Main ID Register152
  - Figure 3-11 Cache Type Register Format153
  - Table 3-6 Cache Type Register Bit Functions153
  - Table 3-7 Results of Access to the Cache Type Register155
  - Table 3-8 Example Cache Type Register Format155
  - Figure 3-12 TCM Status Register Format156
  - Table 3-9 TCM Status Register Bit Functions156
  - Figure 3-13 TLB Type Register Format157
  - Table 3-10 TLB Type Register Bit Functions157
  - Table 3-11 Results of Access to the TLB Type Register157
  - Figure 3-14 Processor Feature Register 0 Format158
  - Table 3-12 Processor Feature Register 0 Bit Functions158
  - Table 3-13 Results of Access to the Processor Feature Register 0159
  - Figure 3-15 Processor Feature Register 1 Format160
  - Table 3-14 Processor Feature Register 1 Bit Functions160
  - Table 3-15 Results of Access to the Processor Feature Register 1160
  - Figure 3-16 Debug Feature Register 0 Format161
  - Table 3-16 Debug Feature Register 0 Bit Functions161
  - Table 3-17 Results of Access to the Debug Feature Register 0161
  - Table 3-18 Auxiliary Feature Register 0 Bit Functions162
  - Table 3-19 Results of Access to the Auxiliary Feature Register 0162
  - Figure 3-17 Memory Model Feature Register 0 Format163
  - Table 3-20 Memory Model Feature Register 0 Bit Functions163
  - Table 3-21 Results of Access to the Memory Model Feature Register 0163
  - Figure 3-18 Memory Model Feature Register 1 Format164
  - Table 3-22 Memory Model Feature Register 1 Bit Functions164
  - Table 3-23 Results of Access to the Memory Model Feature Register 1165
  - Figure 3-19 Memory Model Feature Register 2 Format166
  - Table 3-24 Memory Model Feature Register 2 Bit Functions166
  - Figure 3-20 Memory Model Feature Register 3 Format167
  - Table 3-25 Results of Access to the Memory Model Feature Register 2167
  - Table 3-26 Memory Model Feature Register 3 Bit Functions167
  - Figure 3-21 Instruction Set Attributes Register 0 Format168
  - Table 3-27 Results of Access to the Memory Model Feature Register 3168
  - Table 3-28 Instruction Set Attributes Register 0 Bit Functions168
  - Table 3-29 Results of Access to the Instruction Set Attributes Register 0169
  - Figure 3-22 Instruction Set Attributes Register 1 Format170
  - Table 3-30 Instruction Set Attributes Register 1 Bit Functions170
  - Table 3-31 Results of Access to the Instruction Set Attributes Register 1170
  - Figure 3-23 Instruction Set Attributes Register 2 Format171
  - Table 3-32 Instruction Set Attributes Register 2 Bit Functions171
  - Figure 3-24 Instruction Set Attributes Register 3 Format172
  - Table 3-33 Results of Access to the Instruction Set Attributes Register 2172
  - Table 3-34 Instruction Set Attributes Register 3 Bit Functions173
  - Table 3-35 Results of Access to the Instruction Set Attributes Register 3173
  - Figure 3-25 Instruction Set Attributes Register 4 Format174
  - Table 3-36 Instruction Set Attributes Register 4 Bit Functions174
  - Table 3-37 Results of Access to the Instruction Set Attributes Register 4175
  - Table 3-38 Results of Access to the Instruction Set Attributes Register 5175
  - Figure 3-26 Control Register Format176
  - Figure177
  - Table 3-39 Control Register Bit Functions177
  - Figure179
  - Table 3-40 Results of Access to the Control Register179
  - Table 3-41 Resultant B Bit, U Bit, and EE Bit Values180
  - Figure 3-27 Auxiliary Control Register Format181
  - Table 3-42 Auxiliary Control Register Bit Functions181
  - Table 3-43 Results of Access to the Auxiliary Control Register182
  - Figure 3-28 Coprocessor Access Control Register Format183
  - Table 3-44 Coprocessor Access Control Register Bit Functions183
  - Table 3-45 Results of Access to the Coprocessor Access Control Register183
  - Figure 3-29 Secure Configuration Register Format184
  - Table 3-46 Secure Configuration Register Bit Functions184
  - Table 3-47 Operation of the FW and FIQ Bits185
  - Table 3-48 Operation of the AW and EA Bits185
  - Figure 3-30 Secure Debug Enable Register Format186
  - Table 3-49 Secure Debug Enable Register Bit Functions186
  - Table 3-50 Results of Access to the Coprocessor Access Control Register187
  - Figure 3-31 Non-Secure Access Control Register Format188
  - Table 3-51 Non-Secure Access Control Register Bit Functions188
  - Figure 3-32 Translation Table Base Register 0 Format189
  - Table 3-52 Results of Access to the Auxiliary Control Register189
  - Table 3-53 Translation Table Base Register 0 Bit Functions190
  - Table 3-54 Results of Access to the Translation Table Base Register 0190
  - Figure 3-33 Translation Table Base Register 1 Format191
  - Table 3-55 Translation Table Base Register 1 Bit Functions191
  - Table 3-56 Results of Access to the Translation Table Base Register 1192
  - Figure 3-34 Translation Table Base Control Register Format193
  - Table 3-57 Translation Table Base Control Register Bit Functions193
  - Table 3-58 Results of Access to the Translation Table Base Control Register194
  - Figure 3-35 Domain Access Control Register Format195
  - Table 3-59 Domain Access Control Register Bit Functions195
  - Table 3-60 Results of Access to the Domain Access Control Register195
  - Figure 3-36 Data Fault Status Register Format196
  - Table 3-61 Data Fault Status Register Bit Functions196
  - Figure 3-37 Instruction Fault Status Register Format198
  - Table 3-62 Results of Access to the Data Fault Status Register198
  - Table 3-63 Instruction Fault Status Register Bit Functions199
  - Table 3-64 Results of Access to the Instruction Fault Status Register199
  - Table 3-65 Results of Access to the Fault Address Register200
  - Table 3-66 Results of Access to the Instruction Fault Address Register201
  - Figure 3-38 Cache Operations202
  - Figure 3-39 Cache Operations with MCRR Instructions203
  - Figure 3-40 C7 Format for Set and Index204
  - Table 3-67 Functional Bits of C7 for Set and Index204
  - Table 3-68 Cache Size and S Parameter Dependency204
  - Figure 3-41 C7 Format for MVA205
  - Figure 3-42 Format of C7 for VA205
  - Table 3-69 Functional Bits of C7 for MVA205
  - Table 3-70 Functional Bits of C7 for VA Format206
  - Table 3-71 Cache Operations for Entire Cache206
  - Table 3-72 Cache Operations for Single Lines207
  - Table 3-73 Cache Operations for Address Ranges208
  - Figure209
  - Figure 3-43 Cache Dirty Status Register Format210
  - Table 3-74 Cache Dirty Status Register Bit Functions210
  - Figure 3-44 C7 Format for Flush Branch Target Entry Using MVA211
  - Table 3-75 Cache Operations Flush Functions211
  - Table 3-76 Flush Branch Target Entry Using MVA Bit Functions211
  - Figure 3-45 PA Register Format for Successful Translation212
  - Figure 3-46 PA Register Format for Aborted Translation212
  - Table 3-77 PA Register for Successful Translation Bit Functions212
  - Table 3-78 PA Register for Unsuccessful Translation Bit Functions213
  - Table 3-79 Results of Access to the Data Synchronization Barrier Operation216
  - Table 3-80 Results of Access to the Data Memory Barrier Operation217
  - Table 3-81 Results of Access to the Wait for Interrupt Operation217
  - Table 3-82 Results of Access to the TLB Operations Register218
  - Figure 3-47 TLB Operations Register MVA and ASID Format219
  - Figure 3-48 TLB Operations Register ASID Format219
  - Figure 3-49 Instruction and Data Cache Lockdown Register Formats220
  - Table 3-83 Instruction and Data Cache Lockdown Register Bit Functions220
  - Table 3-84 Results of Access to the Instruction and Data Cache Lockdown Register220
  - Figure 3-50 Data TCM Region Register Format222
  - Table 3-85 Data TCM Region Register Bit Functions222
  - Figure 3-51 Instruction TCM Region Register Format223
  - Table 3-86 Results of Access to the Data TCM Region Register223
  - Table 3-87 Instruction TCM Region Register Bit Functions224
  - Figure 3-52 Data TCM Non-Secure Control Access Register Format225
  - Table 3-88 Results of Access to the Instruction TCM Region Register225
  - Table 3-89 Data TCM Non-Secure Control Access Register Bit Functions226
  - Table 3-90 Effects of NS Items for Data TCM Operation226
  - Figure 3-53 Instruction TCM Non-Secure Control Access Register Format227
  - Table 3-91 Instruction TCM Non-Secure Control Access Register Bit Functions227
  - Table 3-92 Effects of NS Items for Instruction TCM Operation227
  - Figure 3-54 TCM Selection Register Format228
  - Table 3-93 TCM Selection Register Bit Functions228
  - Figure 3-55 Cache Behavior Override Register Format229
  - Table 3-94 Results of Access to the TCM Selection Register229
  - Table 3-95 Cache Behavior Override Register Bit Functions230
  - Table 3-96 Results of Access to the Cache Behavior Override Register230
  - Figure 3-56 TLB Lockdown Register Format232
  - Table 3-97 TLB Lockdown Register Bit Functions232
  - Table 3-98 Results of Access to the TLB Lockdown Register232
  - Figure 3-57 Primary Region Remap Register Format234
  - Table 3-99 Primary Region Remap Register Bit Functions234
  - Figure 3-58 Normal Memory Remap Register Format235
  - Table 3-100 Encoding for the Remapping of the Primary Memory Type235
  - Table 3-101 Normal Memory Remap Register Bit Functions235
  - Table 3-102 Remap Encoding for Inner or Outer Cacheable Attributes236
  - Table 3-103 Results of Access to the Memory Region Remap Registers236
  - Figure 3-59 DMA Identification and Status Registers Format238
  - Table 3-104 DMA Identification and Status Register Bit Functions238
  - Table 3-105 DMA Identification and Status Register Functions238
  - Table 3-106 Results of Access to the DMA Identification and Status Registers239
  - Figure 3-60 DMA User Accessibility Register Format240
  - Table 3-107 DMA User Accessibility Register Bit Functions240
  - Table 3-108 Results of Access to the DMA User Accessibility Register240
  - Figure 3-61 DMA Channel Number Register Format241
  - Table 3-109 DMA Channel Number Register Bit Functions241
  - Table 3-110 Results of Access to the DMA Channel Number Register241
  - Table 3-111 Results of Access to the DMA Enable Registers243
  - Figure 3-62 DMA Control Register Format244
  - Table 3-112 DMA Control Register Bit Functions244
  - Table 3-113 Results of Access to the DMA Control Register245
  - Table 3-114 Results of Access to the DMA Internal Start Address Register246
  - Table 3-115 Results of Access to the DMA External Start Address Register247
  - Table 3-116 Results of Access to the DMA Internal End Address Register248
  - Figure 3-63 DMA Channel Status Register Format249
  - Table 3-117 DMA Channel Status Register Bit Functions249
  - Table 3-118 Results of Access to the DMA Channel Status Register251
  - Figure 3-64 DMA Context ID Register Format252
  - Table 3-119 DMA Context ID Register Bit Functions252
  - Table 3-120 Results of Access to the DMA Context ID Register252
  - Figure 3-65 Secure or Non-Secure Vector Base Address Register Format253
  - Table 3-121 Secure or Non-Secure Vector Base Address Register Bit Functions253
  - Figure 3-66 Monitor Vector Base Address Register Format254
  - Table 3-122 Results of Access to the Secure or Non-Secure Vector Base Address Register254
  - Table 3-123 Monitor Vector Base Address Register Bit Functions255
  - Table 3-124 Results of Access to the Monitor Vector Base Address Register255
  - Figure 3-67 Interrupt Status Register Format256
  - Table 3-125 Interrupt Status Register Bit Functions256
  - Table 3-126 Results of Access to the Interrupt Status Register256
  - Figure 3-68 FCSE PID Register Format258
  - Table 3-127 FCSE PID Register Bit Functions258
  - Table 3-128 Results of Access to the FCSE PID Register258
  - Figure 3-69 Address Mapping with the FCSE PID Register259
  - Figure 3-70 Context ID Register Format260
  - Table 3-129 Context ID Register Bit Functions260
  - Table 3-130 Results of Access to the Context ID Register260
  - Table 3-131 Results of Access to the Thread and Process ID Registers261
  - Figure 3-71 Peripheral Port Memory Remap Register Format262
  - Table 3-132 Peripheral Port Memory Remap Register Bit Functions263
  - Table 3-133 Results of Access to the Peripheral Port Remap Register263
  - Figure 3-72 Secure User and Non-Secure Access Validation Control Register Format264
  - Table 3-134 Secure User and Non-Secure Access Validation Control Register Bit Functions264
  - Figure 3-73 Performance Monitor Control Register Format265
  - Table 3-136 Performance Monitor Control Register Bit Functions266
  - Table 3-137 Performance Monitoring Events267
  - Table 3-138 Results of Access to the Performance Monitor Control Register269
  - Table 3-139 Results of Access to the Cycle Counter Register270
  - Table 3-140 Results of Access to the Count Register 0271
  - Table 3-141 Results of Access to the Count Register 1272
- Table 3-142 System Validation Counter Register Operations272
- Table 3-143 Results of Access to the System Validation Counter Register273
- Figure 3-74 System Validation Counter Register Format for External Debug Request Counter273
- Table 3-144 System Validation Operations Register Functions274
- Table 3-145 Results of Access to the System Validation Operations Register275
- Table 3-146 System Validation Cache Size Mask Register Bit Functions277
- Figure 3-75 System Validation Cache Size Mask Register Format277
- Table 3-147 Results of Access to the System Validation Cache Size Mask Register278
- Table 3-148 TLB Lockdown Index Register Bit Functions281
- Figure 3-76 TLB Lockdown Index Register Format281
- Figure 3-77 TLB Lockdown VA Register Format281
- Table 3-149 TLB Lockdown VA Register Bit Functions282
- Table 3-150 TLB Lockdown PA Register Bit Functions282
- Figure 3-78 TLB Lockdown PA Register Format282
- Table 3-151 Access Permissions APX and AP Bit Fields Encoding283
- Table 3-152 TLB Lockdown Attributes Register Bit Functions283
- Figure 3-79 TLB Lockdown Attributes Register Format283
- Table 3-153 Results of Access to the TLB Lockdown Access Registers284
Chapter 4 Unaligned and Mixed-Endian Data Access Support287
- About Unaligned and Mixed-Endian Support287
- Unaligned Access Support288
- Table 4-1 Unaligned Access Handling289
- Endian Support291
- Figure 4-1 Load Unsigned Byte291
- Figure 4-2 Load Signed Byte291
- Figure 4-3 Store Byte292
- Figure 4-4 Load Unsigned Halfword, Little-Endian292
- Figure 4-5 Load Unsigned Halfword, Big-Endian293
- Figure 4-6 Load Signed Halfword, Little-Endian293
- Figure 4-7 Load Signed Halfword, Big-Endian294
- Figure 4-8 Store Halfword, Little-Endian294
- Figure 4-9 Store Halfword, Big-Endian295
- Figure 4-10 Load Word, Little-Endian295
- Figure 4-11 Load Word, Big-Endian296
- Figure 4-12 Store Word, Little-Endian296
- Figure 4-13 Store Word, Big-Endian297
- Operation of Unaligned Accesses298
- Table 4-2 Memory Access Types298
- Table 4-3 Unalignment Fault Occurrence When Access Behavior Is Architecturally Unpredictable299
- Mixed-Endian Access Support302
- Table 4-4 Legacy Endianness Using CP15 C1302
- Figure302
- Table 4-5 Mixed-Endian Configuration304
- Table 4-6 B Bit, U Bit, and EE Bit Settings304
- Instructions to Reverse Bytes in a General-Purpose Register305
- Instructions to Change the CPSR E Bit306
Chapter 5 Program Flow Prediction307
- About Program Flow Prediction308
- Branch Prediction310
- Return Stack313
- Memory Barriers314
- ARM1176JZF-S IMB Implementation316
Chapter 6 Memory Management Unit319
- About the MMU319
- TLB Organization321
  - Figure321
  - Figure323
- Memory Access Sequence324
- Enabling and Disabling the MMU326
- Memory Access Control328
- Table 6-1 Access Permission Bit Encoding329
- Figure330
- Memory Region Attributes331
- Figure331
- Table 6-2 TEX Field, and C and B Bit Encodings Used in Page Table Formats332
- Table 6-3 Cache Policy Bits333
- Table 6-4 Inner and Outer Cache Policy Implementation Options333
- Table 6-5 Effect of Remapping Memory with TEX Remap = 1334
- Table 6-6 Values that Remap the Shareable Attribute335
- Table 6-7 Primary Region Type Encoding335
- Table 6-8 Inner and Outer Region Remap Encoding335
- Figure336
- Memory Attributes and Types337
- Table 6-9 Memory Attributes337
- Figure340
- Figure 6-1 Memory Ordering Restrictions341
- Table 6-10 Memory Region Backwards Compatibility343
- MMU Aborts344
- MMU Fault Checking346
  - Translation Table Managed TLB Fault Checking Sequence Part 1347
  - Figure347
  - Translation Table Managed TLB Fault Checking Sequence Part 2348
- Fault Status and Address351
- Table 6-11 Fault Status Register Encoding351
- Table 6-12 Summary of Aborts352
- Hardware Page Table Translation353
- Figure 6-4 Backwards-Compatible First-Level Descriptor Format354
- Figure 6-5 Backwards-Compatible Second-Level Descriptor Format355
- Figure 6-6 Backwards-Compatible Section, Supersection, and Page Translation355
- Figure 6-7 Armv6 First-Level Descriptor Formats with Subpages Disabled356
- Figure 6-8 Armv6 Second-Level Descriptor Format357
- Figure 6-9 Armv6 Section, Supersection, and Page Translation358
- MMU Descriptors360
- Table 6-13 Translation Table Size360
- Figure 6-10 Creating a First-Level Descriptor Address361
- Table 6-14 Access Types from First-Level Descriptor Bit Values362
- Translation for a 1MB Section, Armv6 Format363
- Translation for a 1MB Section, Backwards-Compatible Format363
- Table 6-15 Access Types from Second-Level Descriptor Bit Values364
- Generating a Second-Level Page Table Address364
- Figure 6-14 Large Page Table Walk, Armv6 Format365
- Figure 6-15 Large Page Table Walk, Backwards-Compatible Format366
- Figure 6-16 4KB Small Page or 1KB Small Subpage Translations, Backwards-Compatible Format367
- Figure 6-17 4KB Extended Small Page Translations, Armv6 Format368
- Figure 6-18 4KB Extended Small Page or 1KB Extended Small Subpage Translations369
- MMU Software-Accessible Registers370
- Table 6-16 CP15 Register Functions370
- Table 6-17 CP14 Register Functions371
Chapter 7 Level One Memory System373
- About the Level One Memory System373
- Figure373
- Cache Organization374
- Figure374
- Figure 7-1 Level One Cache Block Diagram375
- Tightly-Coupled Memory378
- Table 7-1 TCM Configurations378
- Table 7-2 Access to Non-Secure TCM379
- Table 7-3 Access to Secure TCM379
- Dma381
- TCM and Cache Interactions383
- Table 7-4 Summary of Data Accesses to TCM and Caches385
- Table 7-5 Summary of Instruction Accesses to TCM and Caches386
- Write Buffer387
Chapter 8 Level Two Interface389
- About the Level Two Interface389
- Figure 8-1 Level Two Interconnect Interfaces389
- Table 8-1 AXI Parameters for the Level 2 Interconnect Interfaces390
- Dma Interface392
- Synchronization Primitives393
- AXI Control Signals in the Processor395
- Figure 8-2 Channel Architecture of Reads395
- Figure 8-3 Channel Architecture of Writes395
- Table 8-2 Axlen[3:0] Encoding397
- Table 8-3 Axsize[2:0] Encoding398
- Table 8-4 Axburst[1:0] Encoding398
- Table 8-5 Axlock[1:0] Encoding398
- Table 8-6 Axcache[3:0] Encoding399
- Table 8-7 Axprot[2:0] Encoding399
- Table 8-8 Axsideband[4:1] Encoding400
- Table 8-9 ARSIDEBANDI[4:1] Encoding400
- Instruction Fetch Interface Transfers401
- Table 8-10 AXI Signals for Cacheable Fetches401
- Table 8-11 AXI Signals for Noncacheable Fetches401
- Data Read/Write Interface Transfers402
  - Table 8-12 Linefill Behavior on the AXI Interface402
  - Table 8-13 Noncacheable LDRB403
  - Table 8-14 Noncacheable LDRH403
  - Table 8-15 Noncacheable LDR or LDM1404
  - Table 8-16 Noncacheable LDRD or LDM2404
  - Noncacheable LDRD or LDM2 from Word 7405
  - Table 8-18 Noncacheable LDM3, Strongly Ordered or Device Memory405
  - Table 8-19 Noncacheable LDM3, Noncacheable Memory or Cache Disabled405
- Noncacheable LDM3 from Word 6, or 7405
- Table 8-21 Noncacheable LDM4, Strongly Ordered or Device Memory406
- Table 8-22 Noncacheable LDM4, Noncacheable Memory or Cache Disabled406
- Noncacheable LDM4 from Word 5, 6, or 7406
- Table 8-24 Noncacheable LDM5, Strongly Ordered or Device Memory407
- Table 8-25 Noncacheable LDM5, Noncacheable Memory or Cache Disabled407
- Table 8-27 Noncacheable LDM6, Strongly Ordered or Device Memory407
- Noncacheable LDM5 from Word 4, 5, 6, or 7407
- Table 8-28 Noncacheable LDM6, Noncacheable Memory or Cache Disabled408
- Noncacheable LDM6 from Word 3, 4, 5, 6, or 7408
- Table 8-30 Noncacheable LDM7, Strongly Ordered or Device Memory408
- Table 8-31 Noncacheable LDM7, Noncacheable Memory or Cache Disabled408
- Table 8-32 Noncacheable LDM7 from Word 2, 3, 4, 5, 6, or 7409
- Noncacheable LDM8 from Word 1, 2, 3, 4, 5, 6, or 7409
- Table 8-35 Noncacheable LDM9409
- Table 8-36 Noncacheable LDM10410
- Table 8-37 Noncacheable LDM11410
- Table 8-38 Noncacheable LDM12411
- Table 8-39 Noncacheable LDM13411
- Table 8-40 Noncacheable LDM14411
- Table 8-41 Noncacheable LDM15412
- Table 8-42 Noncacheable LDM16412
- Table 8-43 Half-Line Write-Back413
- Table 8-44 Full-Line Write-Back413
- Table 8-45 Cacheable Write-Through or Noncacheable STRB414
- Table 8-46 Cacheable Write-Through or Noncacheable STRH414
- Table 8-47 Cacheable Write-Through or Noncacheable STR or STM1415
- Cacheable Write-Through or Noncacheable STRD or STM2 to Words 0, 1, 2, 3, 4, 5, or 6416
- Cacheable Write-Through or Noncacheable STM2 to Word 7416
- Cacheable Write-Through or Noncacheable STM3 to Words 0, 1, 2, 3, 4, or 5416
- Cacheable Write-Through or Noncacheable STM3 to Words 6 or 7416
- Cacheable Write-Through or Noncacheable STM4 to Word 0, 1, 2, 3, or 4417
- Cacheable Write-Through or Noncacheable STM4 to Word 5, 6, or 7417
- Cacheable Write-Through or Noncacheable STM5 to Word 0, 1, 2, or 3417
- Cacheable Write-Through or Noncacheable STM5 to Word 4, 5, 6, or 7417
- Cacheable Write-Through or Noncacheable STM6 to Word 0, 1, or 2418
- Cacheable Write-Through or Noncacheable STM6 to Word 3, 4, 5, 6, or 7418
- Cacheable Write-Through or Noncacheable STM7 to Word 0 or 1418
- Cacheable Write-Through or Noncacheable STM7 to Word 2, 3, 4, 5, 6 or 7419
- Cacheable Write-Through or Noncacheable STM8 to Word 0419
- Cacheable Write-Through or Noncacheable STM8 to Word 1, 2, 3, 4, 5, 6, or 7419
- Table 8-62 Cacheable Write-Through or Noncacheable STM9419
- Table 8-63 Cacheable Write-Through or Noncacheable STM10420
- Table 8-64 Cacheable Write-Through or Noncacheable STM11420
- Table 8-65 Cacheable Write-Through or Noncacheable STM12421
- Table 8-66 Cacheable Write-Through or Noncacheable STM13421
- Table 8-67 Cacheable Write-Through or Noncacheable STM14422
- Table 8-68 Cacheable Write-Through or Noncacheable STM15422
- Table 8-69 Cacheable Write-Through or Noncacheable STM16423
- Peripheral Interface Transfers424
- Table 8-70 Example Peripheral Interface Reads and Writes424
- Endianness425
- Figure 8-4 Swizzling of Data and Strobes in BE-32 Big-Endian Configuration425
- Locked Access426
Chapter 9 Clocking and Resets428
- About Clocking and Resets428
- Clocking and Resets with no IEM429
- Figure 9-1 Processor Clocks with no IEM429
- Figure 9-2 Read Latency with no IEM430
- Clocking and Resets with IEM431
- Figure431
- Figure 9-3 Processor Clocks with IEM432
- Figure 9-4 Processor Synchronization with IEM432
- Figure 9-5 Read Latency with IEM434
- Reset Modes436
- Table 9-1 Reset Modes436
- Figure 9-6 Power-On Reset436
Chapter 10 Power Control438
- About Power Control439
- Power Management440
- VFP Shutdown443
- Intelligent Energy Management444
- Figure444
Chapter 11 Coprocessor Interface445
- Figure 10-1 IEM Structure445
- About the Coprocessor Interface447
- Coprocessor Pipeline448
- Table 11-1 Coprocessor Instructions448
- Table 11-2 Coprocessor Control Signals449
- Figure449
- Figure 11-1 Core and Coprocessor Pipelines450
- Figure 11-2 Coprocessor Pipeline and Queues450
- Figure 11-3 Coprocessor Pipeline451
- Table 11-3 Pipeline Stage Update452
- Token Queue Management454
- Figure 11-4 Token Queue Buffers454
- Table 11-4 Addressing of Queue Buffers455
- Figure 11-5 Queue Reading and Writing455
- Figure 11-6 Queue Flushing456
- Token Queues457
- Figure 11-7 Instruction Queue457
- Data Transfer460
- Figure 11-8 Coprocessor Data Transfer460
- Figure 11-9 Instruction Iteration for Loads461
- Figure 11-10 Load Data Buffering462
- Operations464
- Table 11-5 Retirement Conditions465
- Multiple Coprocessors467
Chapter 12 Vectored Interrupt Controller Port469
- About the PL192 Vectored Interrupt Controller469
- About the Processor VIC Port470
- Table 12-1 VIC Port Signals470
- Figure 12-1 Connection of a VIC to the Processor470
- Timing of the VIC Port472
- Figure 12-2 VIC Port Timing Example472
- Interrupt Entry Flowchart474
- Figure 12-3 Interrupt Entry Sequence474
Chapter 13 Debug476
- Debug Systems476
- Figure 13-1 Typical Debug System476
- About the Debug Unit477
- Debug Registers479
- Table 13-1 Terms Used in Register Descriptions479
- Table 13-2 CP14 Debug Register Map479
- Figure 13-2 Debug ID Register Format480
- Table 13-3 Debug ID Register Bit Field Definition481
- Figure481
- Table 13-4 Debug Status and Control Register Bit Field Definitions482
- Figure 13-3 Debug Status and Control Register Format482
- Table 13-5 Data Transfer Register Bit Field Definitions486
- Figure 13-4 DTR Format486
- Figure 13-5 Vector Catch Register Format487
- Table 13-6 Vector Catch Register Bit Field Definitions488
- Table 13-7 Summary of Debug Entry and Exception Conditions488
- Table 13-8 Processor Breakpoint and Watchpoint Registers490
- Table 13-9 Breakpoint Value Registers, Bit Field Definition491
- Table 13-10 Processor Breakpoint Control Registers491
- Figure 13-6 Breakpoint Control Registers, Format491
- Table 13-11 Breakpoint Control Registers, Bit Field Definitions492
- Table 13-12 Meaning of BCR[22:20] Bits493
- Table 13-13 Processor Watchpoint Value Registers494
- Table 13-14 Watchpoint Value Registers, Bit Field Definitions495
- Table 13-15 Processor Watchpoint Control Registers495
- Table 13-16 Watchpoint Control Registers, Bit Field Definitions495
- Figure 13-7 Watchpoint Control Registers, Format495
- Table 13-17 Debug State Cache Control Register Bit Functions497
- Table 13-18 Debug State MMU Control Register Bit Functions498
- CP14 Registers Reset499
- CP14 Debug Instructions500
- Table 13-19 CP14 Debug Instructions500
- Table 13-20 Debug Instruction Execution501
- External Debug Interface502
- Table 13-21 Secure Debug Behavior502
- Changing the Debug Enable Signals505
- Debug Events506
- Table 13-22 Behavior of the Processor on Debug Events507
- Table 13-23 Setting of CP15 Registers on Debug Events508
- Debug Exception509
- Table 13-24 Values in the Link Register after Exceptions510
- 13.10 Debug State511
- Table 13-25 Read PC Value after Debug State Entry513
- Table 13-26 Example Memory Operation Sequence515
- 13.11 Debug Communications Channel516
- 13.12 Debugging in a Cached System517
- 13.13 Debugging in a System with Tlbs518
- 13.14 Monitor Debug-Mode Debugging519
- 13.15 Halting Debug-Mode Debugging524
- 13.16 External Signals526
Chapter 14 Debug Test Access Port528
- Debug Test Access Port and Debug State528
- Figure 14-1 JTAG DBGTAP State Machine Diagram528
- Synchronizing Realview ICE529
- Figure 14-2 Realview ICE Clock Synchronization529
- Entering Debug State530
- Exiting Debug State531
- The DBGTAP Port and Debug Registers532
- Table 14-1 Supported Public Instructions532
- Debug Registers534
- Figure 14-3 Bypass Register Bit Order534
- Figure 14-4 Device ID Code Register Bit Order535
- Figure 14-5 Instruction Register Bit Order535
- Figure 14-6 Scan Chain Select Register Bit Order536
- Figure 14-7 Scan Chain 0 Bit Order537
- Figure 14-8 Scan Chain 1 Bit Order537
- Figure 14-9 Scan Chain 4 Bit Order539
- Figure 14-10 Scan Chain 5 Bit Order, EXTEST Selected541
- Figure 14-11 Scan Chain 5 Bit Order, INTEST Selected541
- Figure 14-12 Scan Chain 6 Bit Order543
- Figure 14-13 Scan Chain 7 Bit Order544
- Table 14-2 Scan Chain 7 Register Map545
- Using the Debug Test Access Port547
- Figure 14-14 Behavior of the Itrsel IR Instruction548
- Debug Sequences555
- Programming Debug Events566
- 14.10 Monitor Debug-Mode Debugging568
Chapter 15 Trace Interface Port569
- About the ETM Interface570
- Table 15-1 Instruction Interface Signals570
- Table 15-2 ETMIACTL[17:0]571
- Table 15-3 ETMIASECCTL[1:0]572
- Table 15-4 Data Address Interface Signals572
- Table 15-5 ETMDACTL[17:0]573
- Table 15-6 Data Value Interface Signals574
- Table 15-7 ETMDDCTL[3:0]574
- Table 15-8 ETMPADV[2:0]574
- Table 15-9 Coprocessor Interface Signals575
- Table 15-10 ETMCPSECCTL[1:0] Format575
- Figure 15-1 ETMCPADDRESS Format575
- Table 15-11 Other Connections576
- Figure576
Chapter 16 Cycle Timings and Interlock Behavior577
- About Cycle Timings and Interlock Behavior578
- Table 16-1 Pipeline Stages579
- Conditional Instructions580
- Table 16-2 Definition of Cycle Timing Terms581
- Register Interlock Examples582
- Table 16-3 Register Interlock Examples582
- Data Processing Instructions583
- Table 16-4 Data Processing Instruction Cycle Timing Behavior if Destination Is Not PC583
- Table 16-5 Data Processing Instruction Cycle Timing Behavior if Destination Is the PC583
- QADD, QDADD, QSUB, and QDSUB Instructions585
- Table 16-6 QADD, QDADD, QSUB, and QDSUB Instruction Cycle Timing Behavior585
- Armv6 Media Data-Processing586
- Table 16-7 Armv6 Media Data-Processing Instructions Cycle Timing Behavior586
- Armv6 Sum of Absolute Differences (SAD)587
- Table 16-8 Armv6 Sum of Absolute Differences Instruction Timing Behavior587
- Table 16-9 Example Interlocks587
- Multiplies588
- Table 16-10 Example Multiply Instruction Cycle Timing Behavior588
- Branches590
- Table 16-11 Branch Instruction Cycle Timing Behavior590
- Processor State Updating Instructions591
- Table 16-12 Processor State Updating Instructions Cycle Timing Behavior591
- 16.10 Single Load and Store Instructions592
- Table 16-13 Cycle Timing Behavior for Stores and Loads, Other than Loads to the PC592
- Table 16-14 Cycle Timing Behavior for Loads to the PC593
- Table 16-15 <Addr_Md_1Cycle> and <Addr_Md_2Cycle> LDR Example Instruction Explanation593
- 16.11 Load and Store Double Instructions595
- Table 16-16 Load and Store Double Instructions Cycle Timing Behavior595
- Table 16-17 <Addr_Md_1Cycle> and <Addr_Md_2Cycle> LDRD Example Instruction Explanation595
- 16.12 Load and Store Multiple Instructions597
- Table 16-18 Cycle Timing Behavior of Load and Store Multiples, Other than Load Multiples Including the PC597
- Table 16-19 Cycle Timing Behavior of Load Multiples, Where the PC Is in the Register List598
- 16.13 RFE and SRS Instructions599
- Table 16-20 RFE and SRS Instructions Cycle Timing Behavior599
- 16.14 Synchronization Instructions600
- Table 16-21 Synchronization Instructions Cycle Timing Behavior600
- 16.15 Coprocessor Instructions601
- Table 16-22 Coprocessor Instructions Cycle Timing Behavior601
- 16.16 SVC, SMC, BKPT, Undefined, and Prefetch Aborted Instructions602
- Table 16-23 SVC, BKPT, Undefined, Prefetch Aborted Instructions Cycle Timing Behavior602
- 16.17 no Operation603
- 16.18 Thumb Instructions604
Chapter 17 AC Characteristics605
- Processor Timing Diagrams606
- Processor Timing Parameters607
- Table 17-1 Global Signals607
- Table 17-2 AXI Signals607
- Table 17-3 Coprocessor Signals609
- Table 17-4 ETM Interface Signals609
- Table 17-5 Interrupt Signals609
- Table 17-6 Debug Interface Signals610
- Table 17-7 Test Signals610
- Table 17-8 Static Configuration Signals610
- Table 17-9 Trustzone Internal Signals611
Chapter 18 Introduction to the VFP Coprocessor612
- About the VFP11 Coprocessor613
- Applications614
- Coprocessor Interface615
- VFP11 Coprocessor Pipelines616
- Figure 18-1 FMAC Pipeline617
- Figure 18-2 DS Pipeline619
- Figure 18-3 LS Pipeline620
- Modes of Operation622
- Short Vector Instructions624
- Parallel Execution of Instructions625
- VFP11 Treatment of Branch Instructions626
- Writing Optimal VFP11 Code627
- 18.10 VFP11 Revision Information628
Chapter 19 The VFP Register File629
- About the Register File630
- Figure630
- Register File Internal Formats631
- Figure 19-1 Single-Precision Data Format631
- Figure 19-2 Double-Precision Data Format632
- Decoding the Register File633
- Figure 19-3 Register File Access633
- Loading Operands from ARM11 Registers634
- Table 19-1 VFP11 MCR Instructions634
- Table 19-2 VFP11 MRC Instructions634
- Table 19-3 VFP11 MCRR Instructions634
- Table 19-4 VFP11 MRRC Instructions635
- Maintaining Consistency in Register Precision636
- Data Transfer between Memory and VFP11 Registers637
- Table 19-5 Single-Precision Data Memory Images and Byte Addresses637
- Table 19-6 Double-Precision Data Memory Images and Byte Addresses637
- Access to Register Banks in CDP Operations638
- Figure 19-4 Register Banks638
- Table 19-7 Single-Precision Three-Operand Register Usage641
- Table 19-8 Single-Precision Two-Operand Register Usage641
- Table 19-9 Double-Precision Three-Operand Register Usage641
- Table 19-10 Double-Precision Two-Operand Register Usage641
Chapter 20 VFP Programmer's Model642
- About the Programmer's Model643
- Compliance with the IEEE 754 Standard644
- Table 20-1 Default Nan Values645
- Table 20-2 Qnan and Snan Handling646
- Armv5Te Coprocessor Extensions649
- Figure 20-1 FMDRR Instruction Format649
- Figure 20-2 FMRRD Instruction Format650
- Figure 20-3 FMSRR Instruction Format651
- Figure 20-4 FMRRS Instruction Format652
- VFP11 System Registers653
- Table 20-3 VFP11 System Registers653
- Table 20-4 Accessing VFP11 System Registers654
- Figure 20-5 Floating-Point System ID Register654
- Table 20-5 FPSID Bit Fields655
- Figure 20-6 Floating-Point Status and Control Register655
- Table 20-6 Encoding of the Floating-Point Status and Control Register656
- Table 20-7 Vector Length and Stride Combinations657
- Table 20-8 Encoding of the Floating-Point Exception Register658
- Figure 20-7 Floating-Point Exception Register658
- Table 20-9 Media and VFP Feature Register 0 Bit Functions660
- Figure 20-8 Media and VFP Feature Register 0 Format660
- Table 20-10 Media and VFP Feature Register 1 Bit Functions661
- Figure 20-9 Media and VFP Feature Register 1 Format661
Chapter 21 VFP Instruction Execution662
- About Instruction Execution663
- Serializing Instructions664
- Interrupting the VFP11 Coprocessor665
- Forwarding666
- Hazards667
- Operation of the Scoreboards668
- Table 21-1 Single-Precision Source Register Locking669
- Table 21-2 Single-Precision Source Register Clearing670
- Table 21-3 Double-Precision Source Register Locking671
- Table 21-4 Double-Precision Source Register Clearing for One-Cycle Instructions672
- Table 21-5 Double-Precision Source Register Clearing for Two-Cycle Instructions672
- Data Hazards in Full-Compliance Mode674
- Copyright © 2004-2009 ARM Limited. All Rights Reserved674
- Table 21-6 FCMPS-FMSTAT RAW Hazard674
- Table 21-7 FLDM-FADDS RAW Hazard675
- Table 21-8 FLDM-Short Vector FADDS RAW Hazard675
- Table 21-9 FMULS-FADDS RAW Hazard676
- Table 21-10 Short Vector FMULS-FLDMS war Hazard676
- Data Hazards in Runfast Mode677
- Table 21-11 Short Vector FMULS-FLDMS war Hazard in Runfast Mode677
- Resource Hazards678
- Table 21-12 FLDM-FLDS-FADDS Resource Hazard679
- Table 21-13 FLDM-Short Vector FMULS Resource Hazard679
- Table 21-14 Short Vector FDIVS-FADDS Resource Hazard680
- 21.10 Parallel Execution681
- Table 21-15 Parallel Execution in All Three Pipelines682
- 21.11 Execution Timing683
- Table 21-16 Throughput and Latency Cycle Counts for VFP11 Instructions683
Chapter 22 VFP Exception Handling684
- About Exception Processing685
- Bounced Instructions686
- Support Code688
- Exception Processing691
- Table 22-1 Exceptional Short Vector FMULD Followed by Load/Store Instructions692
- Table 22-2 Exceptional Short Vector FADDS with a FADDS in the Pretrigger Slot693
- Table 22-3 Exceptional Short Vector FADDD with an FMACS Trigger Instruction694
- Input Subnormal Exception695
- Invalid Operation Exception696
- Table 22-4 Possible Invalid Operation Exceptions696
- Table 22-5 Default Results for Invalid Conversion Inputs697
- Division by Zero Exception698
- Overflow Exception699
- Table 22-6 Rounding Mode Overflow Results699
- Underflow Exception700
- 22.10 Inexact Exception701
- 22.11 Input Exceptions702
- 22.12 Arithmetic Exceptions703
- Table 22-7 LSA and USA Determination703
- Table 22-8 FADD Family Bounce Thresholds704
- Table 22-9 FMUL Family Bounce Thresholds705
- Table 22-10 FDIV Bounce Thresholds706
- Table 22-11 FCVTSD Bounce Thresholds707
- Table 22-12 Single-Precision Float-To-Integer Bounce Thresholds and Stored Results708
- Table 22-13 Double-Precision Float-To-Integer Bounce Thresholds and Stored Results709
Appendix A Signal Descriptions711
- Global Signals712
- Table A-1 Global Signals712
- Static Configuration Signals714
- Table A-2 Static Configuration Signals714
- Trustzone Internal Signals715
- Table A-3 Trustzone Internal Signals715
- Interrupt Signals, Including VIC Interface716
- Table A-4 Interrupt Signals716
- AXI Interface Signals717
- Table A-5 Port Signal Name Suffixes717
- Table A-6 Instruction Read Port AXI Signal Implementation718
- Table A-7 Data Port AXI Signal Implementation719
- Table A-8 Peripheral Port AXI Signal Implementation720
- Table A-9 DMA Port Signals721
- Coprocessor Interface Signals722
- Table A-10 Core to Coprocessor Signals722
- Table A-11 Coprocessor to Core Signals722
- Debug Interface Signals, Including JTAG724
- Table A-12 Debug Interface Signals724
- ETM Interface Signals725
- Table A-13 ETM Interface Signals725
- Test Signals726
- Table A-14 Test Signals726
Appendix B Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences727
- About the Differences between the ARM1136JF-S and ARM1176JZF-S Processors728
- Summary of Differences729
  - B.2 Summary of Differences729
  - Figure730
- Table B-1 TCM for ARM1176JZF-S Processors732
- Table B-2 CP15 C15 Features Common to ARM1136JF-S and ARM1176JZF-S Processors734
- Table B-3 CP15 C15 Only Found in ARM1136JF-S Processors735
- Table C-1 Differences between Issue G and Issue H738
  - Figure751
  - Figure752

ARM ARM1176JZF-S - 16.18 Thumb Instructions

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