ARM ARM1176JZF-S - Figure 2-13 LDREXH Instruction

Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-31
ID012310 Non-Confidential, Unrestricted Access
Operation
if ConditionPassed(cond) then
processor_id = ExecutingProcessor()
if IsExclusiveLocal(processor_id) then
if Shared(Rn)==1 then
physical_address=TLB(Rn)
if IsExclusiveGlobal(physical_address,processor_id,1) then
Memory[Rn,1] = Rm
Rd = 0
ClearByAddress(physical_address,1)
else
Rd =1
else
Memory[Rn,1] = Rm
Rd = 0
else
Rd = 1
ClearExclusiveLocal(processor_id)
2.11.2 Load or Store Halfword Exclusive
These instructions operate on naturally aligned, unsigned data of size halfword:
• The address in memory must be 16-bit aligned, address[0] == b0
When (A,U) == (0,1), (1,0) or (1,1) in CP15 register 1, the instruction generates alignment
faults if this condition is not met.
For more information, see Operation of unaligned accesses on page 4-13.
• The transaction must be a single access or indivisible burst on bus widths < 16 bits
For AXI based systems, the exclusive access signal, AxPROT[4], must remain asserted
throughout the burst where AxSIZE <
0x1 .
The LDREXH and STREXH instructions share the same data monitors as the LDREX and
STREX instructions, a local and a global monitor for each processor, for shared memory
support.
LDREXH
Figure 2-13 shows the format of the Load Register Halfword Exclusive, LDREXH, instruction.
Figure 2-13 LDREXH instruction
Syntax
LDREXH{<cond>} <Rd>, [<Rn>]
Operation
if ConditionPassed(cond) then
processor_id = ExecutingProcessor()
Rd = Memory[Rn,2]
if Shared(Rn) ==1 then
physical_address=TLB(Rn)
MarkExclusiveGlobal(physical_address,processor_id,2)
MarkExclusiveLocal(processor_id)
SBOCond
31 28 27 21 20 19 15 12 11 7 4 3 0
0 0 0 1 1 1 1 1 Rn Rd SBO 1 0 0 1
16 8