ARM ARM1176JZF-S User Manual

Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-28
ID012310 Non-Confidential, Unrestricted Access
8.5.24 Cacheable Write-Through or Noncacheable STR or STM1
Table 8-47 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for STRs or STM1s over the Data Read/Write Interface.
8.5.25 Cacheable Write-Through or Noncacheable STRD or STM2
Table 8-48 on page 8-29 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW,
and AWLENRW for STM2s to words 0 to 6 over the Data Read/Write Interface.
Table 8-47 Cacheable Write-Through or Noncacheable STR or STM1
Address[4:0]
AWADDRR
W
AWBURSTR
W
AWSIZERW AWLENRW WSTRBRW
0x00 , byte 0, word 0 0x00 Incr 32-bit 1 data transfer b0000 1111
0x01 , byte 1 0x00 Incr 32-bit 1 data transfer b0000 1110
0x04 Incr 8-bit 1 data transfer b0001 0000
0x02 , byte 2 0x02 Incr 16-bit 1 data transfer b0000 1100
0x04 Incr 16-bit 1 data transfer b0011 0000
0x03 , byte 3 0x03 Incr 8-bit 1 data transfer b0000 1000
0x04 Incr 32-bit 1 data transfer b0111 0000
0x04 , byte 4, word 1 0x04 Incr 32-bit 1 data transfer b1111 0000
0x05 , byte 5 0x04 Incr 32-bit 1 data transfer b1110 0000
0x08 Incr 8-bit 1 data transfer b0000 0001
0x06 , byte 6 0x06 Incr 16-bit 1 data transfer b1100 0000
0x08 Incr 16-bit 1 data transfer b0000 0011
0x07 , byte 7 0x07 Incr 8-bit 1 data transfer b1000 0000
0x08 Incr 32-bit 1 data transfer b0000 0111
0x08 , byte 8, word 2 0x08 Incr 32-bit 1 data transfer b0000 1111
0x0C , word 3 0x0C Incr 32-bit 1 data transfer b1111 0000
0x10 , word 4 0x10 Incr 32-bit 1 data transfer b0000 1111
0x14 , word 5 0x14 Incr 32-bit 1 data transfer b1111 0000
0x18 , word 6 0x18 Incr 32-bit 1 data transfer b0000 1111
0x1C , word 7 0x1C Incr 32-bit 1 data transfer b1111 0000

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English