System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-69
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3.2.20 c6, Watchpoint Fault Address Register
Access to the Watchpoint Fault Address register through the system control coprocessor is
deprecated, see CP14 c6, Watchpoint Fault Address Register (WFAR) on page 13-12.
3.2.21 c6, Instruction Fault Address Register
The purpose of the Instruction Fault Address Register (IFAR) is to hold the address of
instructions that cause a prefetch abort.
The IFAR is:
•in CP15 c6
• a 32-bit read/write register banked for Secure and Non-secure worlds
• accessible in privileged modes only.
The Instruction Fault Address Register bits [31:0] contain the Instruction Fault MVA. The reset
value is 0.
Table 3-66 lists the results of attempted access for each mode.
To use the IFAR read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c6
• CRm set to c0
• Opcode_2 set to 2.
For example:
MRC p15, 0, <Rd>, c6, c0, 2 ; Read Instruction Fault Address Register
MCR p15, 0, <Rd>, c6, c0, 2 ; Write Instruction Fault Address Register
A write to this register sets the IFAR to the value of the data written. This is useful for a debugger
to restore the value of the IFAR.
3.2.22 c7, Cache operations
The purpose of c7 is to:
• control these operations:
— clean and invalidate instruction and data caches, including range operations
— prefetch instruction cache line
— Flush Prefetch Buffer
— flush branch target address cache
— virtual to physical address translation.
• implement the Data Synchronization Barrier (DSB) operation
• implement the Data Memory Barrier (DMB) operation
Table 3-66 Results of access to the Instruction Fault Address Register
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Secure data Secure data Non-secure data Non-secure data Undefined exception
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