System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-64
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MRC p15, 0, <Rd>, c3, c0, 0 ; Read Domain Access Control Register
MCR p15, 0, <Rd>, c3, c0, 0 ; Write Domain Access Control Register
3.2.17 c5, Data Fault Status Register
The purpose of the Data Fault Status Register is to hold the source of the last data fault.
Table 3-61 lists the purposes of the individual bits in the Data Fault Status Register.
The Data Fault Status Register is:
•in CP15 c5
• a 32-bit read/write register banked for Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-36 shows the bit arrangement in the Data Fault Status Register.
Figure 3-36 Data Fault Status Register format
Table 3-61 shows how the bit values correspond with the Data Fault Status Register functions.
S
D
0
UNP/SBZ
31 8 7 4 3 0
Domain Status
9
0S
1011
R
W
1213
Table 3-61 Data Fault Status Register bit functions
Bits
Field
name
Function
[31:13] - UNP/SBZ.
[12] SD Indicates if an AXI Decode or Slave error caused an abort. This is only valid for external
aborts. For all other aborts this Should Be Zero. See Fault status and address on
page 6-34:
0 = AXI Decode error caused the abort, reset value
1 = AXI Slave error caused the abort.
[11] RW Indicates whether a read or write access caused an abort:
0 = Read access caused the abort, reset value
1 = Write access caused the abort.
[10] S Part of the Status field. See Bits [3:0] in this table. The reset value is 0.
[9:8] - Always read as 0. Writes ignored.
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