AC Characteristics
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 17-6
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Table 17-6 lists the debug timing parameters.
Table 17-7 lists the test port timing parameters.
Table 17-8 lists the static configuration signal port timing parameters.
Table 17-6 Debug interface signals
Name Minimum input delay Maximum input delay%
TCK Clock uncertainty 20
JTAGSYNCBYPAS
S
Clock uncertainty 20
DBGnTRST Clock uncertainty 60
TDI Clock uncertainty 20
TMS Clock uncertainty 20
EDBGRQ Clock uncertainty 60
DBGEN Clock uncertainty 60
DBGVERSION[3:0] Clock uncertainty 50
DBGMANID[10:0] Clock uncertainty 50
SPIDEN Clock uncertainty 60
SPNIDEN Clock uncertainty 60
Table 17-7 Test signals
Name Minimum input delay Maximum input delay%
SE Clock uncertainty 20
RSTBYPASS Clock uncertainty 20
MTESTON Clock uncertainty 60
MBISTDIN[63:0] Clock uncertainty 60
MBISTADDR[12:0] Clock uncertainty 60
MBISTCE[19:0] Clock uncertainty 60
MBISTWE[7:0] Clock uncertainty 60
MBISTDOUT[63:0] Clock uncertainty 40
Table 17-8 Static configuration signals
Name Minimum input delay Maximum input delay%
BIGENDINIT Clock uncertainty 60
INITRAM Clock uncertainty 60
UBITINIT Clock uncertainty 60
VINITHI Clock uncertainty 60
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